Fast and compact sequential circuits through the information-driven circuit synthesis

L. Jozwiak; A.S. Slusarczyk; A. Chojnacki

doi:10.1109/DSD.2001.952116

Fast and compact sequential circuits through the information-driven circuit synthesis

L. Jozwiak
, A.S. Slusarczyk
, A. Chojnacki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.

Original language	English
Title of host publication	Proceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE Computer Society
Pages	46-53
ISBN (Print)	0-7695-1239-9
DOIs	https://doi.org/10.1109/DSD.2001.952116
Publication status	Published - 2001
Event	4th Euromicro Symposium on Digital System Design (DSD 2001) - Warsaw, Poland Duration: 4 Sept 2001 → 6 Sept 2001

Conference

Conference	4th Euromicro Symposium on Digital System Design (DSD 2001)
Abbreviated title	DSD2 001
Country/Territory	Poland
City	Warsaw
Period	4/09/01 → 6/09/01

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10.1109/DSD.2001.952116

Cite this

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title = "Fast and compact sequential circuits through the information-driven circuit synthesis",

abstract = "Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25\% smaller and 30\% faster than those synthesized by another state-of-the-art tools.",

author = "L. Jozwiak and A.S. Slusarczyk and A. Chojnacki",

year = "2001",

doi = "10.1109/DSD.2001.952116",

language = "English",

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booktitle = "Proceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001",

publisher = "IEEE Computer Society",

address = "United States",

note = "4th Euromicro Symposium on Digital System Design (DSD 2001), DSD2 001 ; Conference date: 04-09-2001 Through 06-09-2001",

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Jozwiak, L, Slusarczyk, AS & Chojnacki, A 2001, Fast and compact sequential circuits through the information-driven circuit synthesis. in Proceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001. IEEE Computer Society, Los Alamitos, CA, USA, pp. 46-53, 4th Euromicro Symposium on Digital System Design (DSD 2001), Warsaw, Poland, 4/09/01. https://doi.org/10.1109/DSD.2001.952116

Fast and compact sequential circuits through the information-driven circuit synthesis. / Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.
Proceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001. Los Alamitos, CA, USA: IEEE Computer Society, 2001. p. 46-53.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Fast and compact sequential circuits through the information-driven circuit synthesis

AU - Jozwiak, L.

AU - Slusarczyk, A.S.

AU - Chojnacki, A.

PY - 2001

Y1 - 2001

N2 - Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.

AB - Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.

U2 - 10.1109/DSD.2001.952116

DO - 10.1109/DSD.2001.952116

M3 - Conference contribution

SN - 0-7695-1239-9

SP - 46

EP - 53

BT - Proceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001

PB - IEEE Computer Society

CY - Los Alamitos, CA, USA

T2 - 4th Euromicro Symposium on Digital System Design (DSD 2001)

Y2 - 4 September 2001 through 6 September 2001

ER -

Fast and compact sequential circuits through the information-driven circuit synthesis

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