Failure Analysis and Test Solutions for Low-Power SRAMs

Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Nabil Badereddine

doi:10.1109/ATS.2011.97

Failure Analysis and Test Solutions for Low-Power SRAMs

Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

Original language	English
Title of host publication	2011 Asian Test Symposium
Publisher	Institute of Electrical and Electronics Engineers
Pages	459-460
Number of pages	2
ISBN (Print)	978-1-4577-1984-4
DOIs	https://doi.org/10.1109/ATS.2011.97
Publication status	Published - 29 Dec 2011
Externally published	Yes
Event	20th IEEE Asian Test Symposium (ATS 2011) - New Delhi, India Duration: 20 Nov 2011 → 23 Nov 2011

Conference

Conference	20th IEEE Asian Test Symposium (ATS 2011)
Country/Territory	India
City	New Delhi
Period	20/11/11 → 23/11/11

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10.1109/ATS.2011.97

Cite this

@inproceedings{f6869672ebcd40b186af75c9b21b309b,

title = "Failure Analysis and Test Solutions for Low-Power SRAMs",

abstract = "Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.",

author = "Zordan, {Leonardo Bonet} and Alberto Bosio and Luigi Dilillo and Patrick Girard and Serge Pravossoudovitch and Aida Todri and Arnaud Virazel and Nabil Badereddine",

year = "2011",

month = dec,

day = "29",

doi = "10.1109/ATS.2011.97",

language = "English",

isbn = "978-1-4577-1984-4",

pages = "459--460",

booktitle = "2011 Asian Test Symposium",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "20th IEEE Asian Test Symposium (ATS 2011) ; Conference date: 20-11-2011 Through 23-11-2011",

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TY - GEN

T1 - Failure Analysis and Test Solutions for Low-Power SRAMs

AU - Zordan, Leonardo Bonet

AU - Bosio, Alberto

AU - Dilillo, Luigi

AU - Girard, Patrick

AU - Pravossoudovitch, Serge

AU - Todri, Aida

AU - Virazel, Arnaud

AU - Badereddine, Nabil

PY - 2011/12/29

Y1 - 2011/12/29

N2 - Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

AB - Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

U2 - 10.1109/ATS.2011.97

DO - 10.1109/ATS.2011.97

M3 - Conference contribution

SN - 978-1-4577-1984-4

SP - 459

EP - 460

BT - 2011 Asian Test Symposium

PB - Institute of Electrical and Electronics Engineers

T2 - 20th IEEE Asian Test Symposium (ATS 2011)

Y2 - 20 November 2011 through 23 November 2011

ER -

Failure Analysis and Test Solutions for Low-Power SRAMs

Abstract

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