Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Xiaolong Zhang; Yuanqing Cheng; Weisheng Zhao; Youguang Zhang; Aida Todri-Sanial

doi:10.1109/ICSICT.2014.7021342

Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Xiaolong Zhang, Yuanqing Cheng, Weisheng Zhao, Youguang Zhang, Aida Todri-Sanial

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.

Original language	English
Title of host publication	Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
Editors	Jia Zhou, Ting-Ao Tang
Publisher	Institute of Electrical and Electronics Engineers
ISBN (Electronic)	9781479932962
DOIs	https://doi.org/10.1109/ICSICT.2014.7021342
Publication status	Published - 23 Jan 2014
Externally published	Yes
Event	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 - Guilin, China Duration: 28 Oct 2014 → 31 Oct 2014

Conference

Conference	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
Country/Territory	China
City	Guilin
Period	28/10/14 → 31/10/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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Cite this

Zhang, X., Cheng, Y., Zhao, W., Zhang, Y., & Todri-Sanial, A. (2014). Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design. In J. Zhou, & T.-A. Tang (Eds.), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 Article 7021342 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICSICT.2014.7021342

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abstract = "Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.",

author = "Xiaolong Zhang and Yuanqing Cheng and Weisheng Zhao and Youguang Zhang and Aida Todri-Sanial",

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Zhang, X, Cheng, Y, Zhao, W, Zhang, Y & Todri-Sanial, A 2014, Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design. in J Zhou & T-A Tang (eds), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014., 7021342, Institute of Electrical and Electronics Engineers, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Guilin, China, 28/10/14. https://doi.org/10.1109/ICSICT.2014.7021342

Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design. / Zhang, Xiaolong; Cheng, Yuanqing; Zhao, Weisheng et al.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. ed. / Jia Zhou; Ting-Ao Tang. Institute of Electrical and Electronics Engineers, 2014. 7021342.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.

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Zhang X, Cheng Y, Zhao W, Zhang Y, Todri-Sanial A. Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design. In Zhou J, Tang TA, editors, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Institute of Electrical and Electronics Engineers. 2014. 7021342 doi: 10.1109/ICSICT.2014.7021342

Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

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