Exploiting expendable process-margins in DRAMs for run-time performance optimizations

K. Chandrasekar, S.L.M. Goossens, C. Weis, M.L.P.J. Koedam, K.B. Akesson, N. Wehn, K.G.W. Goossens

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Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct DRAM functionality under worst-case operating conditions. Unfortunately, with technology scaling these timing margins have become large and very pessimistic for a majority of the manufactured DRAMs. While run-time variations are specific to operating conditions and as a result, their margins difficult to optimize, process variations are manufacturing-time effects and excessive process-margins can be reduced at run-time, on a per-device basis, if properly identified. In this paper, we propose a generic post-manufacturing performance characterization methodology for DRAMs that identifies this excess in process-margins for any given DRAM device at runtime, while retaining the requisite margins for voltage (noise) and temperature variations. By doing so, the methodology ascertains the actual impact of process-variations on the particular DRAM device and optimizes its access latencies (timings), thereby improving its overall performance. We evaluate this methodology on 48 DDR3 devices (from 12 DIMMs) and verify the derived timings under worst-case operating conditions, showing up to 33.3% and 25.9% reduction in DRAM read and write latencies, respectively.
Original languageEnglish
Title of host publicationProceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2014), 24-28 March 2014, Dresden, Germany
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-3-9815370-2-4
Publication statusPublished - 2014
Event17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) - ICC, Dresden, Germany
Duration: 24 Mar 201428 Mar 2014
Conference number: 17


Conference17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014)
Abbreviated titleDATE 2014
City Dresden
Internet address


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