TY - JOUR
T1 - Evaluation of DVFS techniques on modern HPC processors and accelerators for energy-aware applications
AU - Calore, Enrico
AU - Gabbana, Alessandro
AU - Schifano, Sebastiano Fabio
AU - Tripiccione, Raffaele
N1 - Publisher Copyright:
Copyright © 2017 John Wiley & Sons, Ltd.
PY - 2017/6/25
Y1 - 2017/6/25
N2 - Energy efficiency is becoming increasingly important for computing systems, in particular for large scale High Performance Computing (HPC) facilities. In this work, we evaluate, from a user perspective, the use of Dynamic Voltage and Frequency Scaling techniques, assisted by the power and energy monitoring capabilities of modern processors to tune applications for energy efficiency. We run selected kernels and a full HPC application on 2 high-end processors widely used in the HPC context, namely, an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on an HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model and derive a number of energy saving strategies, which can be easily adopted on recent high-end HPC systems for generic applications.
AB - Energy efficiency is becoming increasingly important for computing systems, in particular for large scale High Performance Computing (HPC) facilities. In this work, we evaluate, from a user perspective, the use of Dynamic Voltage and Frequency Scaling techniques, assisted by the power and energy monitoring capabilities of modern processors to tune applications for energy efficiency. We run selected kernels and a full HPC application on 2 high-end processors widely used in the HPC context, namely, an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on an HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model and derive a number of energy saving strategies, which can be easily adopted on recent high-end HPC systems for generic applications.
KW - application
KW - DVFS
KW - energy-aware
KW - GPU
KW - HPC
KW - user
UR - http://www.scopus.com/inward/record.url?scp=85016574309&partnerID=8YFLogxK
U2 - 10.1002/cpe.4143
DO - 10.1002/cpe.4143
M3 - Article
AN - SCOPUS:85016574309
SN - 1532-0626
VL - 29
JO - Concurrency and Computation : Practice & Experience
JF - Concurrency and Computation : Practice & Experience
IS - 12
M1 - e4143
ER -