Evaluating template-based instruction compression on Transport Triggered Architectures

J.E. Heikkinen; T. Rantanen; A.G.M. Cilio; J. Takala; H. Corporaal

Evaluating template-based instruction compression on Transport Triggered Architectures

J.E. Heikkinen, T. Rantanen, A.G.M. Cilio, J. Takala, H. Corporaal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proceedings of the International Workshop on System-on-Chip for Real-Time Applications
Pages	192-195
Publication status	Published - 2003
Event	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), June 30-July 2, 2003, Calgary, Canada - Calgary, Canada Duration: 30 Jun 2003 → 2 Jul 2003

Workshop

Workshop	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), June 30-July 2, 2003, Calgary, Canada
Abbreviated title	IWSOC 2003
Country	Canada
City	Calgary
Period	30/06/03 → 2/07/03
Other

Cite this

@inproceedings{8c9c3e5dd0ac4c1eba192b803d6c8a46,

title = "Evaluating template-based instruction compression on Transport Triggered Architectures",

author = "J.E. Heikkinen and T. Rantanen and A.G.M. Cilio and J. Takala and H. Corporaal",

year = "2003",

language = "English",

isbn = "0-7695-1944-X",

pages = "192--195",

booktitle = "Proceedings of the International Workshop on System-on-Chip for Real-Time Applications",

note = "3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), June 30-July 2, 2003, Calgary, Canada, IWSOC 2003 ; Conference date: 30-06-2003 Through 02-07-2003",

}

Heikkinen, JE, Rantanen, T, Cilio, AGM, Takala, J & Corporaal, H 2003, Evaluating template-based instruction compression on Transport Triggered Architectures. in Proceedings of the International Workshop on System-on-Chip for Real-Time Applications. pp. 192-195, 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), June 30-July 2, 2003, Calgary, Canada, Calgary, Canada, 30/06/03.

Evaluating template-based instruction compression on Transport Triggered Architectures. / Heikkinen, J.E.; Rantanen, T.; Cilio, A.G.M.; Takala, J.; Corporaal, H.

Proceedings of the International Workshop on System-on-Chip for Real-Time Applications. 2003. p. 192-195.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Evaluating template-based instruction compression on Transport Triggered Architectures

AU - Heikkinen, J.E.

AU - Rantanen, T.

AU - Cilio, A.G.M.

AU - Takala, J.

AU - Corporaal, H.

PY - 2003

Y1 - 2003

M3 - Conference contribution

SN - 0-7695-1944-X

SP - 192

EP - 195

BT - Proceedings of the International Workshop on System-on-Chip for Real-Time Applications

T2 - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), June 30-July 2, 2003, Calgary, Canada

Y2 - 30 June 2003 through 2 July 2003

ER -