Energy efficient microprocessor platform based on instructional level parallelism

H. Fatemi (Inventor), A. Kapoor (Inventor), J. Pineda de Gyvez (Inventor)

Research output: PatentPatent publication

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Abstract

Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.

Original languageEnglish
Patent numberUS2013232359
IPCG06F 15/ 76 A I
Priority date1/03/12
Publication statusPublished - 5 Sep 2013

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