In a modern processor architecture the register ??le (RF) consumes considerable amount of power. Therefore it is important to reduce the RF accesses when designing an energy e??cient architecture. It is well-known that with datapath exposed to software, the transport-triggered architectures (TTAs) can substantially reduce the RF tra??c. In this paper, we analyze the potential of using MOVE-Pro, a TTAbased processor architecture. And we propose the compiler back-end for MOVE-Pro which can generate code that saves energy consumption by performing energy aware instruction scheduling to reduce RF accesses. The proposed architecture and compiler design is exible. In the experiments we compare the proposed architecture with a RISC processor with the same resource, and achieve a reduction of RF accesses by up to 80%, which results in up to 11% saving in total core power. Meanwhile the dynamic cycle count remains almost the same as the reference processor, which means energy is saved without compromising performance.
|Title of host publication||Proceedings of the 9th workshop on Optimizations for DSP and Embedded Systems (ODES'11), 2 April 2011, Chamonix, France|
|Publication status||Published - 2011|
|Event||conference; ODES'11, Chamonix, France; 2011-04-02; 2011-04-02 - |
Duration: 2 Apr 2011 → 2 Apr 2011
|Conference||conference; ODES'11, Chamonix, France; 2011-04-02; 2011-04-02|
|Period||2/04/11 → 2/04/11|
|Other||ODES'11, Chamonix, France|