Energy consumption in embedded systems is strongly dominated by instruction memory organizations. Based on this, any architectural enhancement introduced in this component will produce a significant reduction of the total energy budget of the system. Loop buffering is an effective scheme to reduce the energy consumption of the instruction memory organization. In this paper, a novel classification of architectural enhancements based on the use of loop buffer concept is presented. Using this classification, an energy design space exploration is performed to show the impact in the energy consumption on different application scenarios. From gate-level simulations, the energy analysis demonstrates that the instruction level paralellism of the system brings not only improvements in performance, but also improvements in the energy consumption of the system. The increase in instruction level paralellism makes easy the adaptation of the sizes of the loop buffers to the sizes of the loops that form the application, because gives more freedom to combine the execution of the loops that form the application.
|Title of host publication||Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010|
|Publisher||IEEE Computer Society|
|Publication status||Published - 1 Jan 2012|
|Event||2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, (IWIA 2010) - Hilo, United States|
Duration: 17 Jan 2010 → 19 Jan 2010
|Conference||2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, (IWIA 2010)|
|Period||17/01/10 → 19/01/10|