Energy-Efficiency Evaluation of Intel KNL for HPC Workloads

Enrico Calore; Alessandro Gabbana; Sebastiano Fabio Schifano; Raffaele Tripiccione

doi:10.3233/978-1-61499-843-3-733

Energy-Efficiency Evaluation of Intel KNL for HPC Workloads

Enrico Calore, Alessandro Gabbana, Sebastiano Fabio Schifano, Raffaele Tripiccione

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

In this work we focus on energy performance of the Knights Landing Xeon Phi, the latest many-core architecture processor introduced by Intel for the HPC market. We take into account the 64-core Xeon Phi 7230, and analyze the computing and energy efficiency using both the on-chip MCDRAM and the off-chip DDR4 memory as main storage for the application data domain. As a benchmark application we use a Lattice Boltzmann code heavily optimized for this architecture, and implemented using different memory data layouts to store the data-domain. We then assess the energy consumption using different data-layouts, memory configurations (DDR4 or MCDRAM), and number of threads per core.

Original language	English
Title of host publication	Parallel Computing is Everywhere
Editors	Sanzio Bassini, Marco Danelutto, Patrizio Dazzi, Gerhard R. Joubert, Frans Peters
Publisher	IOS Press
Pages	733-742
Number of pages	10
ISBN (Electronic)	978-1-61499-843-3
ISBN (Print)	978-1-61499-842-6
DOIs	https://doi.org/10.3233/978-1-61499-843-3-733
Publication status	Published - 2018
Externally published	Yes

Publication series

Name	Advances in Parallel Computing
Volume	32
ISSN (Print)	0927-5452
ISSN (Electronic)	1879-808X

Keywords

Energy
HPC
KNL
Lattice Boltzmann
MCDRAM
Memory

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.3233/978-1-61499-843-3-733

Cite this

@inproceedings{bbc74180c587463196836ab180797d11,

title = "Energy-Efficiency Evaluation of Intel KNL for HPC Workloads",

abstract = "In this work we focus on energy performance of the Knights Landing Xeon Phi, the latest many-core architecture processor introduced by Intel for the HPC market. We take into account the 64-core Xeon Phi 7230, and analyze the computing and energy efficiency using both the on-chip MCDRAM and the off-chip DDR4 memory as main storage for the application data domain. As a benchmark application we use a Lattice Boltzmann code heavily optimized for this architecture, and implemented using different memory data layouts to store the data-domain. We then assess the energy consumption using different data-layouts, memory configurations (DDR4 or MCDRAM), and number of threads per core.",

keywords = "Energy, HPC, KNL, Lattice Boltzmann, MCDRAM, Memory",

author = "Enrico Calore and Alessandro Gabbana and Schifano, {Sebastiano Fabio} and Raffaele Tripiccione",

note = "Publisher Copyright: {\textcopyright} 2018 The authors and IOS Press.",

year = "2018",

doi = "10.3233/978-1-61499-843-3-733",

language = "English",

isbn = "978-1-61499-842-6 ",

series = "Advances in Parallel Computing",

publisher = "IOS Press",

pages = "733--742",

editor = "Sanzio Bassini and Marco Danelutto and Patrizio Dazzi and Joubert, {Gerhard R.} and Frans Peters",

booktitle = "Parallel Computing is Everywhere",

address = "Netherlands",

}

Energy-Efficiency Evaluation of Intel KNL for HPC Workloads. / Calore, Enrico; Gabbana, Alessandro; Schifano, Sebastiano Fabio et al.
Parallel Computing is Everywhere. ed. / Sanzio Bassini; Marco Danelutto; Patrizio Dazzi; Gerhard R. Joubert; Frans Peters. IOS Press, 2018. p. 733-742 (Advances in Parallel Computing; Vol. 32).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Energy-Efficiency Evaluation of Intel KNL for HPC Workloads

AU - Calore, Enrico

AU - Gabbana, Alessandro

AU - Schifano, Sebastiano Fabio

AU - Tripiccione, Raffaele

PY - 2018

Y1 - 2018

N2 - In this work we focus on energy performance of the Knights Landing Xeon Phi, the latest many-core architecture processor introduced by Intel for the HPC market. We take into account the 64-core Xeon Phi 7230, and analyze the computing and energy efficiency using both the on-chip MCDRAM and the off-chip DDR4 memory as main storage for the application data domain. As a benchmark application we use a Lattice Boltzmann code heavily optimized for this architecture, and implemented using different memory data layouts to store the data-domain. We then assess the energy consumption using different data-layouts, memory configurations (DDR4 or MCDRAM), and number of threads per core.

AB - In this work we focus on energy performance of the Knights Landing Xeon Phi, the latest many-core architecture processor introduced by Intel for the HPC market. We take into account the 64-core Xeon Phi 7230, and analyze the computing and energy efficiency using both the on-chip MCDRAM and the off-chip DDR4 memory as main storage for the application data domain. As a benchmark application we use a Lattice Boltzmann code heavily optimized for this architecture, and implemented using different memory data layouts to store the data-domain. We then assess the energy consumption using different data-layouts, memory configurations (DDR4 or MCDRAM), and number of threads per core.

KW - Energy

KW - HPC

KW - KNL

KW - Lattice Boltzmann

KW - MCDRAM

KW - Memory

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DO - 10.3233/978-1-61499-843-3-733

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AN - SCOPUS:85043600516

SN - 978-1-61499-842-6

T3 - Advances in Parallel Computing

SP - 733

EP - 742

BT - Parallel Computing is Everywhere

A2 - Bassini, Sanzio

A2 - Danelutto, Marco

A2 - Dazzi, Patrizio

A2 - Joubert, Gerhard R.

A2 - Peters, Frans

PB - IOS Press

ER -

Energy-Efficiency Evaluation of Intel KNL for HPC Workloads

Abstract

Publication series

Keywords

UN SDGs

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