Abstract
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today’s ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined
functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked ICs (SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are being tested(‘module-under-test’, MUT); we refer to the modules currently not being tested as ‘neighbors’. The switching activity of the MUT(s) can be controlled by ATPG constraints, but the switching activity of the neighboring modules is typically not controlled. In this work, we present two key elements for an approach to con13431trol the switching activity of both MUT(s) and neighboring modules. The first is a toggle analysis tool, that determines the switching activity of a module in either functional or test mode on the basis of a Value Change Dump (.vcd) file generated during gate-level Verilog netlist simulation. The second element is a programmable on-chip toggle generator, for which we present both its hardware scheme, as well as an algorithm to program it to achieve any target switching activity. For each module, the toggle analysis
tool can be used to determine the switching activity in functional
mode, which then forms the target for the ATPG tool when the
module is a MUT, or for its embedded toggle generator while
the module is in its role as neighbor.
functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked ICs (SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are being tested(‘module-under-test’, MUT); we refer to the modules currently not being tested as ‘neighbors’. The switching activity of the MUT(s) can be controlled by ATPG constraints, but the switching activity of the neighboring modules is typically not controlled. In this work, we present two key elements for an approach to con13431trol the switching activity of both MUT(s) and neighboring modules. The first is a toggle analysis tool, that determines the switching activity of a module in either functional or test mode on the basis of a Value Change Dump (.vcd) file generated during gate-level Verilog netlist simulation. The second element is a programmable on-chip toggle generator, for which we present both its hardware scheme, as well as an algorithm to program it to achieve any target switching activity. For each module, the toggle analysis
tool can be used to determine the switching activity in functional
mode, which then forms the target for the ATPG tool when the
module is a MUT, or for its embedded toggle generator while
the module is in its role as neighbor.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation 2017 |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-8 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-5090-6462-5 |
| DOIs | |
| Publication status | Published - 27 Sept 2017 |
| Event | 27th International Symposium on Power and Timing Modeling, optimization and Simulation (PATMOS 2017) - Thessaloniki, Greece Duration: 25 Sept 2017 → 27 Sept 2017 Conference number: 27 http://patmos2017.web.auth.gr/ |
Conference
| Conference | 27th International Symposium on Power and Timing Modeling, optimization and Simulation (PATMOS 2017) |
|---|---|
| Abbreviated title | PATMOS 2017 |
| Country/Territory | Greece |
| City | Thessaloniki |
| Period | 25/09/17 → 27/09/17 |
| Internet address |