Efficient wrapper/TAM co-optimization for large SOCs

Vikram Iyengar, Krishnendu Chakrabarty, Erik J. Marinissen

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

67 Citations (Scopus)


Core test wrappers and test access mechanisms (TAMs) are important components of a system-on-chip (SOC) test architecture. Wrapper/TAM co-optimization is necessary to minimize the SOC testing time. Most prior research in wrapper/TAM design has addressed wrapper design and TAM optimization as separate problems, thereby leading to results that are sub-optimal. We present a fast heuristic technique for wrapper/TAM co-optimization, and demonstrate its scalability for several industrial SOCs. This extends recent work on exact methods for wrapper/TAM co-optimization based on integer linear programming and exhaustive enumeration. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to the testing times obtained using exact methods. Moreover more than two orders of magnitude reduction can be obtained in the CPU time compared to exact methods. Furthermore, we are now able to design efficient test access architectures with a larger number of TAMs.
Original languageEnglish
Title of host publicationProceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages8
ISBN (Print)0-7695-1471-5
Publication statusPublished - 2002
Externally publishedYes
Event5th Design, Automation and Test in Europe Conference and Exhibition (DATE 2002) - Paris, France
Duration: 4 Mar 20028 Mar 2002


Conference5th Design, Automation and Test in Europe Conference and Exhibition (DATE 2002)
Abbreviated titleDATE 2002


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