Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an integer linear programming problem, which is solved to optimality in the second step. In this paper, we concentrate on the constraint derivation task. We present two new constraint derivation algorithms, one of which is more memory efficient and the other more run-time efficient. We show that the run-time efficient algorithm makes it possible to minimize the area of a huge standard cell network, possibly representing a complete IC, within acceptable run-time limits.
|Title of host publication||Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994)|
|Publisher||Institute of Electrical and Electronics Engineers|
|Number of pages||6|
|Publication status||Published - 1994|
Werf, van der, A., Meerbergen, van, J., Aarts, E. H. L., Verhaegh, W. F. J., & Lippens, P. E. R. (1994). Efficient timing constraint derivation for optimally retiming high speed processing units. In Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994) (pp. 48-53). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISHLS.1994.302342