Efficient timing constraint derivation for optimally retiming high speed processing units

A. Werf, van der; J. Meerbergen, van; E.H.L. Aarts; W.F.J. Verhaegh; P.E.R. Lippens

doi:10.1109/ISHLS.1994.302342

Efficient timing constraint derivation for optimally retiming high speed processing units

A. Werf, van der, J. Meerbergen, van, E.H.L. Aarts, W.F.J. Verhaegh, P.E.R. Lippens

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

Abstract

Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an integer linear programming problem, which is solved to optimality in the second step. In this paper, we concentrate on the constraint derivation task. We present two new constraint derivation algorithms, one of which is more memory efficient and the other more run-time efficient. We show that the run-time efficient algorithm makes it possible to minimize the area of a huge standard cell network, possibly representing a complete IC, within acceptable run-time limits.

Original language	English
Title of host publication	Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994)
Publisher	Institute of Electrical and Electronics Engineers
Pages	48-53
Number of pages	6
ISBN (Print)	0-8186-5785-5
DOIs	https://doi.org/10.1109/ISHLS.1994.302342
Publication status	Published - 1994

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Werf, van der, A., Meerbergen, van, J., Aarts, E. H. L., Verhaegh, W. F. J., & Lippens, P. E. R. (1994). Efficient timing constraint derivation for optimally retiming high speed processing units. In Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994) (pp. 48-53). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISHLS.1994.302342

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title = "Efficient timing constraint derivation for optimally retiming high speed processing units",

abstract = "Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an integer linear programming problem, which is solved to optimality in the second step. In this paper, we concentrate on the constraint derivation task. We present two new constraint derivation algorithms, one of which is more memory efficient and the other more run-time efficient. We show that the run-time efficient algorithm makes it possible to minimize the area of a huge standard cell network, possibly representing a complete IC, within acceptable run-time limits.",

author = "{Werf, van der}, A. and {Meerbergen, van}, J. and E.H.L. Aarts and W.F.J. Verhaegh and P.E.R. Lippens",

year = "1994",

doi = "10.1109/ISHLS.1994.302342",

language = "English",

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pages = "48--53",

booktitle = "Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994)",

publisher = "Institute of Electrical and Electronics Engineers",

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Werf, van der, A, Meerbergen, van, J, Aarts, EHL, Verhaegh, WFJ & Lippens, PER 1994, Efficient timing constraint derivation for optimally retiming high speed processing units. in Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994). Institute of Electrical and Electronics Engineers, pp. 48-53. https://doi.org/10.1109/ISHLS.1994.302342

Efficient timing constraint derivation for optimally retiming high speed processing units. / Werf, van der, A.; Meerbergen, van, J.; Aarts, E.H.L. et al.

Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994). Institute of Electrical and Electronics Engineers, 1994. p. 48-53.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Efficient timing constraint derivation for optimally retiming high speed processing units

AU - Werf, van der, A.

AU - Meerbergen, van, J.

AU - Aarts, E.H.L.

AU - Verhaegh, W.F.J.

AU - Lippens, P.E.R.

PY - 1994

Y1 - 1994

N2 - Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an integer linear programming problem, which is solved to optimality in the second step. In this paper, we concentrate on the constraint derivation task. We present two new constraint derivation algorithms, one of which is more memory efficient and the other more run-time efficient. We show that the run-time efficient algorithm makes it possible to minimize the area of a huge standard cell network, possibly representing a complete IC, within acceptable run-time limits.

AB - Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an integer linear programming problem, which is solved to optimality in the second step. In this paper, we concentrate on the constraint derivation task. We present two new constraint derivation algorithms, one of which is more memory efficient and the other more run-time efficient. We show that the run-time efficient algorithm makes it possible to minimize the area of a huge standard cell network, possibly representing a complete IC, within acceptable run-time limits.

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M3 - Conference contribution

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BT - Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994)

PB - Institute of Electrical and Electronics Engineers

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Werf, van der A, Meerbergen, van J, Aarts EHL, Verhaegh WFJ, Lippens PER. Efficient timing constraint derivation for optimally retiming high speed processing units. In Proceedings of the 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994). Institute of Electrical and Electronics Engineers. 1994. p. 48-53 doi: 10.1109/ISHLS.1994.302342

Efficient timing constraint derivation for optimally retiming high speed processing units

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