Efficient test access mechanism optimization for system-on-chip

V. Iyengar, K. Chakrabarty, E.J. Marinissen

Research output: Contribution to journalArticleAcademicpeer-review

48 Citations (Scopus)

Abstract

Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scalability for several industrial SOCs. Since the TAM optimization problem is NP-hard, recently proposed methods based on integer linear programming and exhaustive enumeration can be used to design limited test architectures with only a very small number of TAMs in a reasonable amount of time. In this paper, we explore a larger solution-space to design efficient test architectures with more TAMs. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to or lower than the testing times obtained using enumeration. Moreover, significant reduction can be obtained in the CPU time compared to enumeration.
Original languageEnglish
Pages (from-to)635-643
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume22
Issue number5
DOIs
Publication statusPublished - May 2003
Externally publishedYes

Keywords

  • core-based systems
  • heuristic methods
  • system-on-chip
  • test access mechanism
  • testing time

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