Efficient simulation of power MOS transistors

In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and transistor networks and benefits from the sparsity of the conductance matrix. We also investigate a large resistor network which is a part of the power MOS transistor model and find out which existing reduction methods for resistor networks deliver significant reduction in the amount of resistors.