Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

Y. Bi; P.J.A. Harpe; N.P. Meijs, van der

doi:10.1109/ASPDAC.2011.5722262

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

Y. Bi, P.J.A. Harpe, N.P. Meijs, van der

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design

Original language	English
Title of host publication	Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	61-66
ISBN (Print)	978-1-4244-7515-5
DOIs	https://doi.org/10.1109/ASPDAC.2011.5722262
Publication status	Published - 2011

Access to Document

10.1109/ASPDAC.2011.5722262

Cite this

Bi, Y., Harpe, P. J. A., & Meijs, van der, N. P. (2011). Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. In Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan (pp. 61-66). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASPDAC.2011.5722262

@inproceedings{67ed705406b545ff84f8b1dc2778a896,

title = "Efficient sensitivity-based capacitance modeling for systematic and random geometric variations",

abstract = "This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design",

author = "Y. Bi and P.J.A. Harpe and {Meijs, van der}, N.P.",

year = "2011",

doi = "10.1109/ASPDAC.2011.5722262",

language = "English",

isbn = "978-1-4244-7515-5",

pages = "61--66",

booktitle = "Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Bi, Y, Harpe, PJA & Meijs, van der, NP 2011, Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. in Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan. Institute of Electrical and Electronics Engineers, Piscataway, pp. 61-66. https://doi.org/10.1109/ASPDAC.2011.5722262

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. / Bi, Y.; Harpe, P.J.A.; Meijs, van der, N.P.
Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 61-66.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

AU - Bi, Y.

AU - Harpe, P.J.A.

AU - Meijs, van der, N.P.

PY - 2011

Y1 - 2011

N2 - This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design

AB - This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design

U2 - 10.1109/ASPDAC.2011.5722262

DO - 10.1109/ASPDAC.2011.5722262

M3 - Conference contribution

SN - 978-1-4244-7515-5

SP - 61

EP - 66

BT - Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Bi Y, Harpe PJA, Meijs, van der NP. Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. In Proceedings of the 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2011, Yokohama, Japan. Piscataway: Institute of Electrical and Electronics Engineers. 2011. p. 61-66 doi: 10.1109/ASPDAC.2011.5722262

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

Abstract

Access to Document

Fingerprint

Cite this