Efficient multiple constant multiplication using DSP blocks in FPGA

Ahmet Can Mert; Hasan Azgin; Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/FPL.2018.00063

Efficient multiple constant multiplication using DSP blocks in FPGA

Ahmet Can Mert
, Hasan Azgin
, Ercan Kalali
, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

Abstract

Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8%.

Original language	English
Title of host publication	2018 28th International Conference on Field Programmable Logic and Applications (FPL)
Publisher	Institute of Electrical and Electronics Engineers
Pages	331-334
Number of pages	4
ISBN (Electronic)	978-1-5386-8517-4
DOIs	https://doi.org/10.1109/FPL.2018.00063
Publication status	Published - 6 Dec 2018
Externally published	Yes
Event	28th International Conference on Field Programmable Logic and Applications, FPL 2018 - Dublin, Ireland Duration: 27 Aug 2018 → 30 Aug 2018 Conference number: 28

Conference

Conference	28th International Conference on Field Programmable Logic and Applications, FPL 2018
Abbreviated title	FPL 2018
Country/Territory	Ireland
City	Dublin
Period	27/08/18 → 30/08/18

Keywords

MCM
FPGA
DSP Block
HEVC

Access to Document

10.1109/FPL.2018.00063

Cite this

@inproceedings{fa30b037ba6d443dbc0a00f3a315a8ea,

title = "Efficient multiple constant multiplication using DSP blocks in FPGA",

abstract = "Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8\%.",

keywords = "MCM, FPGA, DSP Block, HEVC",

author = "Mert, \{Ahmet Can\} and Hasan Azgin and Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 28th International Conference on Field Programmable Logic and Applications, FPL 2018, FPL 2018 ; Conference date: 27-08-2018 Through 30-08-2018",

year = "2018",

month = dec,

day = "6",

doi = "10.1109/FPL.2018.00063",

language = "English",

pages = "331--334",

booktitle = "2018 28th International Conference on Field Programmable Logic and Applications (FPL)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Mert, AC, Azgin, H, Kalali, E & Hamzaoglu, I 2018, Efficient multiple constant multiplication using DSP blocks in FPGA. in 2018 28th International Conference on Field Programmable Logic and Applications (FPL)., 8533518, Institute of Electrical and Electronics Engineers, pp. 331-334, 28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, 27/08/18. https://doi.org/10.1109/FPL.2018.00063

Efficient multiple constant multiplication using DSP blocks in FPGA. / Mert, Ahmet Can; Azgin, Hasan; Kalali, Ercan et al.
2018 28th International Conference on Field Programmable Logic and Applications (FPL). Institute of Electrical and Electronics Engineers, 2018. p. 331-334 8533518.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Efficient multiple constant multiplication using DSP blocks in FPGA

AU - Mert, Ahmet Can

AU - Azgin, Hasan

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 28

PY - 2018/12/6

Y1 - 2018/12/6

N2 - Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8%.

AB - Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8%.

KW - MCM

KW - FPGA

KW - DSP Block

KW - HEVC

UR - https://www.scopus.com/pages/publications/85060313473

U2 - 10.1109/FPL.2018.00063

DO - 10.1109/FPL.2018.00063

M3 - Conference contribution

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EP - 334

BT - 2018 28th International Conference on Field Programmable Logic and Applications (FPL)

PB - Institute of Electrical and Electronics Engineers

T2 - 28th International Conference on Field Programmable Logic and Applications, FPL 2018

Y2 - 27 August 2018 through 30 August 2018

ER -

Efficient multiple constant multiplication using DSP blocks in FPGA

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Keywords

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