Efficient damage sensitivity analysis in advanced Cu/Low-k bond pad structures using area release energy

For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of Ultra Low-K (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken.For the thermo-mechanical design of IC back-end structures, an experience based/trial-and-error approach has been mainly used in the past. This is not only time and money consuming, but also inherently troubles the inclusion of packaging requirements in the earlier stages of back-end process development. Due to the reduced design margins and shorter time-to-market, this trail-and-error approach is not sufficient anymore and novel methodology based on advanced simulation and optimization techniques is required. With this virtual prototyping and qualification methodology thermo-mechanical reliability can be dealt with already in the design phase including the interaction with packaging and qualification processes.This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori.The method is applied to advanced IC back-end structures, revealing the critical locations at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in a finite element code. In this way, effects of e.g. packaging and wire bond loading at global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-k back-end structures. The obtained results are in good agreement with experimental observations.