Efficient Architecture Exploration of a Clustered Loop

T. Aa, van der, M. Jayapala, H. Corporaal, G. Deconinck

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proceedings of the Internation Workshop on Optimizations for DSPS and Embedded Ssytems
Publication status	Published - 2006
Event	conference; ODES 2006, New York, USA; 2006-03-26; 2006-03-29 - Duration: 26 Mar 2006 → 29 Mar 2006

Cite this

@inproceedings{91ac659b6f4b492784d73ed8d2a4384b,

title = "Efficient Architecture Exploration of a Clustered Loop",

author = "{Aa, van der}, T. and M. Jayapala and H. Corporaal and G. Deconinck",

year = "2006",

language = "English",

booktitle = "Proceedings of the Internation Workshop on Optimizations for DSPS and Embedded Ssytems",

note = "conference; ODES 2006, New York, USA; 2006-03-26; 2006-03-29 ; Conference date: 26-03-2006 Through 29-03-2006",

}

TY - GEN

T1 - Efficient Architecture Exploration of a Clustered Loop

AU - Aa, van der, T.

AU - Jayapala, M.

AU - Corporaal, H.

AU - Deconinck, G.

PY - 2006

Y1 - 2006

M3 - Conference contribution

BT - Proceedings of the Internation Workshop on Optimizations for DSPS and Embedded Ssytems

T2 - conference; ODES 2006, New York, USA; 2006-03-26; 2006-03-29

Y2 - 26 March 2006 through 29 March 2006

ER -