Effective System Level Liveness Verification

Alexander Fedotov; Jeroen J.A. Keiren; Julien Schmaltz

doi:10.34727/2020/isbn.978-3-85448-042-6_7

Effective System Level Liveness Verification

Alexander Fedotov, Jeroen J.A. Keiren, Julien Schmaltz

Formal System Analysis

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

The language xMAS has been designed by Intel with the purpose of modelling and verification of hardware. Recently, the language was extended with finite state machines to make it more expressive [19]. Furthermore, it was shown how to prove liveness of such extended xMAS networks [19]. Unfortunately, we demonstrate that the proof technique is unsound. We provide an alternative approach which we have carefully proven to be correct. Moreover, we show that our approach scales very well, which makes it possible to prove liveness properties at the system level. In particular, we show that using our approach, it is possible to verify a power control architecture composed of 1299 state machines representing 50 power domains where each domain contains 5 master and 5 slave devices. Proving liveness of this system takes less than 10 minutes.

Original language	English
Title of host publication	Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design, FMCAD 2020
Editors	Alexander Ivrii, Ofer Strichman, Warren A. Hunt, Georg Weissenbacher
Publisher	Institute of Electrical and Electronics Engineers
Pages	7-15
Number of pages	9
ISBN (Electronic)	9783854480426
DOIs	https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_7
Publication status	Published - 21 Sep 2020

Keywords

Formal verification
communication networks
finite state machines
liveness

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10.34727/2020/isbn.978-3-85448-042-6_7

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Fedotov, A., Keiren, J. J. A., & Schmaltz, J. (2020). Effective System Level Liveness Verification. In A. Ivrii, O. Strichman, W. A. Hunt, & G. Weissenbacher (Eds.), Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design, FMCAD 2020 (pp. 7-15). [9283645] Institute of Electrical and Electronics Engineers. https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_7

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abstract = "The language xMAS has been designed by Intel with the purpose of modelling and verification of hardware. Recently, the language was extended with finite state machines to make it more expressive [19]. Furthermore, it was shown how to prove liveness of such extended xMAS networks [19]. Unfortunately, we demonstrate that the proof technique is unsound. We provide an alternative approach which we have carefully proven to be correct. Moreover, we show that our approach scales very well, which makes it possible to prove liveness properties at the system level. In particular, we show that using our approach, it is possible to verify a power control architecture composed of 1299 state machines representing 50 power domains where each domain contains 5 master and 5 slave devices. Proving liveness of this system takes less than 10 minutes.",

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Effective System Level Liveness Verification. / Fedotov, Alexander ; Keiren, Jeroen J.A.; Schmaltz, Julien.

Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design, FMCAD 2020. ed. / Alexander Ivrii; Ofer Strichman; Warren A. Hunt; Georg Weissenbacher. Institute of Electrical and Electronics Engineers, 2020. p. 7-15 9283645.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Effective System Level Liveness Verification

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AU - Keiren, Jeroen J.A.

AU - Schmaltz, Julien

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N2 - The language xMAS has been designed by Intel with the purpose of modelling and verification of hardware. Recently, the language was extended with finite state machines to make it more expressive [19]. Furthermore, it was shown how to prove liveness of such extended xMAS networks [19]. Unfortunately, we demonstrate that the proof technique is unsound. We provide an alternative approach which we have carefully proven to be correct. Moreover, we show that our approach scales very well, which makes it possible to prove liveness properties at the system level. In particular, we show that using our approach, it is possible to verify a power control architecture composed of 1299 state machines representing 50 power domains where each domain contains 5 master and 5 slave devices. Proving liveness of this system takes less than 10 minutes.

AB - The language xMAS has been designed by Intel with the purpose of modelling and verification of hardware. Recently, the language was extended with finite state machines to make it more expressive [19]. Furthermore, it was shown how to prove liveness of such extended xMAS networks [19]. Unfortunately, we demonstrate that the proof technique is unsound. We provide an alternative approach which we have carefully proven to be correct. Moreover, we show that our approach scales very well, which makes it possible to prove liveness properties at the system level. In particular, we show that using our approach, it is possible to verify a power control architecture composed of 1299 state machines representing 50 power domains where each domain contains 5 master and 5 slave devices. Proving liveness of this system takes less than 10 minutes.

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BT - Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design, FMCAD 2020

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Effective System Level Liveness Verification

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