Effective In-Situ chip health monitoring with selective monitor insertion along timing paths

Hadi Ahmadi Balef; Hamed Fatemi; Kees Goossens; José Pineda De Gyvez

doi:10.1145/3194554.3194563

Effective In-Situ chip health monitoring with selective monitor insertion along timing paths

Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda De Gyvez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to ∼11X compared to endpoint insertion techniques. The observability to delay degradation is ∼8X better with our approach, compared to techniques with straight monitor placement at intermediate points.

Original language	English
Title of host publication	GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery, Inc
Chapter	Session 9
Pages	213-218
Number of pages	6
Volume	Part F137141
ISBN (Electronic)	9781450357241
DOIs	https://doi.org/10.1145/3194554.3194563
Publication status	Published - 30 May 2018
Event	28th Great Lakes Symposium on VLSI (GLSVLSI2018) - Chicago, United States Duration: 23 May 2018 → 25 May 2018 Conference number: 28 http://www.glsvlsi.org/

Conference

Conference	28th Great Lakes Symposium on VLSI (GLSVLSI2018)
Abbreviated title	GLVLSI2018
Country/Territory	United States
City	Chicago
Period	23/05/18 → 25/05/18
Internet address	http://www.glsvlsi.org/

Keywords

CMOS variability
Digital circuit
In-situ delay monitoring
Reliability
Digital Circuit
In-Situ Delay Monitoring
CMOS Variability

Access to Document

10.1145/3194554.3194563

Cite this

@inproceedings{5fb270736b0b4e2fa137ba8d4855f464,

title = "Effective In-Situ chip health monitoring with selective monitor insertion along timing paths",

abstract = "In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to ∼11X compared to endpoint insertion techniques. The observability to delay degradation is ∼8X better with our approach, compared to techniques with straight monitor placement at intermediate points.",

keywords = "CMOS variability, Digital circuit, In-situ delay monitoring, Reliability, Digital Circuit, In-Situ Delay Monitoring, CMOS Variability",

author = "Balef, {Hadi Ahmadi} and Hamed Fatemi and Kees Goossens and {De Gyvez}, {Jos{\'e} Pineda}",

year = "2018",

month = may,

day = "30",

doi = "10.1145/3194554.3194563",

language = "English",

volume = "Part F137141",

pages = "213--218",

booktitle = "GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI",

publisher = "Association for Computing Machinery, Inc",

address = "United States",

note = "28th Great Lakes Symposium on VLSI (GLSVLSI2018), GLVLSI2018 ; Conference date: 23-05-2018 Through 25-05-2018",

url = "http://www.glsvlsi.org/",

}

Balef, HA, Fatemi, H, Goossens, K & De Gyvez, JP 2018, Effective In-Situ chip health monitoring with selective monitor insertion along timing paths. in GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI. vol. Part F137141, Association for Computing Machinery, Inc, pp. 213-218, 28th Great Lakes Symposium on VLSI (GLSVLSI2018), Chicago, Illinois, United States, 23/05/18. https://doi.org/10.1145/3194554.3194563

Effective In-Situ chip health monitoring with selective monitor insertion along timing paths. / Balef, Hadi Ahmadi; Fatemi, Hamed; Goossens, Kees et al.
GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI. Vol. Part F137141 Association for Computing Machinery, Inc, 2018. p. 213-218.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Effective In-Situ chip health monitoring with selective monitor insertion along timing paths

AU - Balef, Hadi Ahmadi

AU - Fatemi, Hamed

AU - Goossens, Kees

AU - De Gyvez, José Pineda

N1 - Conference code: 28

PY - 2018/5/30

Y1 - 2018/5/30

N2 - In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to ∼11X compared to endpoint insertion techniques. The observability to delay degradation is ∼8X better with our approach, compared to techniques with straight monitor placement at intermediate points.

AB - In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to ∼11X compared to endpoint insertion techniques. The observability to delay degradation is ∼8X better with our approach, compared to techniques with straight monitor placement at intermediate points.

KW - CMOS variability

KW - Digital circuit

KW - In-situ delay monitoring

KW - Reliability

KW - Digital Circuit

KW - In-Situ Delay Monitoring

KW - CMOS Variability

UR - http://www.scopus.com/inward/record.url?scp=85049425385&partnerID=8YFLogxK

U2 - 10.1145/3194554.3194563

DO - 10.1145/3194554.3194563

M3 - Conference contribution

AN - SCOPUS:85049425385

VL - Part F137141

SP - 213

EP - 218

BT - GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI

PB - Association for Computing Machinery, Inc

T2 - 28th Great Lakes Symposium on VLSI (GLSVLSI2018)

Y2 - 23 May 2018 through 25 May 2018

ER -

Effective In-Situ chip health monitoring with selective monitor insertion along timing paths

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this