Effective In-Situ chip health monitoring with selective monitor insertion along timing paths

Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda De Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to ∼11X compared to endpoint insertion techniques. The observability to delay degradation is ∼8X better with our approach, compared to techniques with straight monitor placement at intermediate points.

Original languageEnglish
Title of host publicationGLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery, Inc
ChapterSession 9
Pages213-218
Number of pages6
VolumePart F137141
ISBN (Electronic)9781450357241
DOIs
Publication statusPublished - 30 May 2018
Event28th Great Lakes Symposium on VLSI (GLSVLSI2018) - Chicago, United States
Duration: 23 May 201825 May 2018
Conference number: 28
http://www.glsvlsi.org/

Conference

Conference28th Great Lakes Symposium on VLSI (GLSVLSI2018)
Abbreviated titleGLVLSI2018
CountryUnited States
CityChicago
Period23/05/1825/05/18
Internet address

Keywords

  • CMOS variability
  • Digital circuit
  • In-situ delay monitoring
  • Reliability
  • Digital Circuit
  • In-Situ Delay Monitoring
  • CMOS Variability

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