Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Xinhui Lai; Maksim Jenihhin; Georgios Selimis; Sven Goossens; Roel Maes; Kolin Paul

doi:10.1109/VLSI-SOC46417.2020.9344071

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Xinhui Lai, Maksim Jenihhin, Georgios Selimis, Sven Goossens, Roel Maes, Kolin Paul

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

Physical Unclonable Functions (PUFs) are gaining attention in the cryptography community because of the ability to efficiently harness the intrinsic variability in the manufacturing process. However, this means that they are noisy devices and require error correction mechanisms, e.g., by employing Fuzzy Extractors (FEs). Recent works demonstrated that applying FEs for error correction may enable new opportunities to break the PUFs if no countermeasures are taken. In this paper, we address an attack model on FEs hardware implementations and provide a solution for early identification of the timing Side-Channel Attack (SCA) vulnerabilities which can be exploited by physical fault injection. The significance of this work stems from the fact that FEs are an essential building block in the implementations of PUF-enabled devices. The information leaked through the timing side-channel during the error correction process can reveal the FE input data and thereby can endanger revealing secrets. Therefore, it is very important to identify the potential leakages early in the process during RTL design. Experimental results based on RTL analysis of several Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon decoders for PUF-enabled devices with FEs demonstrate the feasibility of the proposed methodology.

Original language	English
Title of host publication	2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020
Publisher	Institute of Electrical and Electronics Engineers
Pages	16-21
Number of pages	6
ISBN (Electronic)	978-1-7281-5409-1
DOIs	https://doi.org/10.1109/VLSI-SOC46417.2020.9344071
Publication status	Published - 10 Feb 2021
Externally published	Yes
Event	2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) - Salt Lake City, United States Duration: 5 Oct 2020 → 7 Oct 2020

Conference

Conference	2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)
Country/Territory	United States
City	Salt Lake City
Period	5/10/20 → 7/10/20

Keywords

Reed-Solomon codes
Side-channel attacks
Very large scale integration
Physical unclonable function
Iron
Timing
Error correction

Access to Document

10.1109/VLSI-SOC46417.2020.9344071

Cite this

Lai, X., Jenihhin, M., Selimis, G., Goossens, S., Maes, R., & Paul, K. (2021). Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. In 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020 (pp. 16-21). Article 9344071 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSI-SOC46417.2020.9344071

@inproceedings{6f26830835cd46f198917e64bf1b2165,

title = "Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices",

abstract = "Physical Unclonable Functions (PUFs) are gaining attention in the cryptography community because of the ability to efficiently harness the intrinsic variability in the manufacturing process. However, this means that they are noisy devices and require error correction mechanisms, e.g., by employing Fuzzy Extractors (FEs). Recent works demonstrated that applying FEs for error correction may enable new opportunities to break the PUFs if no countermeasures are taken. In this paper, we address an attack model on FEs hardware implementations and provide a solution for early identification of the timing Side-Channel Attack (SCA) vulnerabilities which can be exploited by physical fault injection. The significance of this work stems from the fact that FEs are an essential building block in the implementations of PUF-enabled devices. The information leaked through the timing side-channel during the error correction process can reveal the FE input data and thereby can endanger revealing secrets. Therefore, it is very important to identify the potential leakages early in the process during RTL design. Experimental results based on RTL analysis of several Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon decoders for PUF-enabled devices with FEs demonstrate the feasibility of the proposed methodology.",

keywords = "Reed-Solomon codes, Side-channel attacks, Very large scale integration, Physical unclonable function, Iron, Timing, Error correction",

author = "Xinhui Lai and Maksim Jenihhin and Georgios Selimis and Sven Goossens and Roel Maes and Kolin Paul",

year = "2021",

month = feb,

day = "10",

doi = "10.1109/VLSI-SOC46417.2020.9344071",

language = "English",

pages = "16--21",

booktitle = "2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) ; Conference date: 05-10-2020 Through 07-10-2020",

}

Lai, X, Jenihhin, M, Selimis, G, Goossens, S, Maes, R & Paul, K 2021, Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. in 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020., 9344071, Institute of Electrical and Electronics Engineers, pp. 16-21, 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), Salt Lake City, United States, 5/10/20. https://doi.org/10.1109/VLSI-SOC46417.2020.9344071

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. / Lai, Xinhui; Jenihhin, Maksim; Selimis, Georgios et al.
2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020. Institute of Electrical and Electronics Engineers, 2021. p. 16-21 9344071.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

AU - Lai, Xinhui

AU - Jenihhin, Maksim

AU - Selimis, Georgios

AU - Goossens, Sven

AU - Maes, Roel

AU - Paul, Kolin

PY - 2021/2/10

Y1 - 2021/2/10

N2 - Physical Unclonable Functions (PUFs) are gaining attention in the cryptography community because of the ability to efficiently harness the intrinsic variability in the manufacturing process. However, this means that they are noisy devices and require error correction mechanisms, e.g., by employing Fuzzy Extractors (FEs). Recent works demonstrated that applying FEs for error correction may enable new opportunities to break the PUFs if no countermeasures are taken. In this paper, we address an attack model on FEs hardware implementations and provide a solution for early identification of the timing Side-Channel Attack (SCA) vulnerabilities which can be exploited by physical fault injection. The significance of this work stems from the fact that FEs are an essential building block in the implementations of PUF-enabled devices. The information leaked through the timing side-channel during the error correction process can reveal the FE input data and thereby can endanger revealing secrets. Therefore, it is very important to identify the potential leakages early in the process during RTL design. Experimental results based on RTL analysis of several Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon decoders for PUF-enabled devices with FEs demonstrate the feasibility of the proposed methodology.

AB - Physical Unclonable Functions (PUFs) are gaining attention in the cryptography community because of the ability to efficiently harness the intrinsic variability in the manufacturing process. However, this means that they are noisy devices and require error correction mechanisms, e.g., by employing Fuzzy Extractors (FEs). Recent works demonstrated that applying FEs for error correction may enable new opportunities to break the PUFs if no countermeasures are taken. In this paper, we address an attack model on FEs hardware implementations and provide a solution for early identification of the timing Side-Channel Attack (SCA) vulnerabilities which can be exploited by physical fault injection. The significance of this work stems from the fact that FEs are an essential building block in the implementations of PUF-enabled devices. The information leaked through the timing side-channel during the error correction process can reveal the FE input data and thereby can endanger revealing secrets. Therefore, it is very important to identify the potential leakages early in the process during RTL design. Experimental results based on RTL analysis of several Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon decoders for PUF-enabled devices with FEs demonstrate the feasibility of the proposed methodology.

KW - Reed-Solomon codes

KW - Side-channel attacks

KW - Very large scale integration

KW - Physical unclonable function

KW - Iron

KW - Timing

KW - Error correction

U2 - 10.1109/VLSI-SOC46417.2020.9344071

DO - 10.1109/VLSI-SOC46417.2020.9344071

M3 - Conference contribution

SP - 16

EP - 21

BT - 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020

PB - Institute of Electrical and Electronics Engineers

T2 - 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)

Y2 - 5 October 2020 through 7 October 2020

ER -

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this