Dynamic time-slot allocation for QoS enabled networks on chip.

T.M. Marescaux, B. Bricke, P. Debacker, V. Nollet, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

20 Citations (Scopus)

Abstract

MP-SoCs are expected to require complex communication architectures such as NoCs. This paper presents, to our knowledge, the first algorithm to dynamically perform routing and allocation of guaranteed communication resources on NoCs that provide QoS with TDMA techniques. We test the efficiency of our algorithm by allocating the communication channels required for an application composed of a 3D pipeline and an MPEG-2 decoder/encoder video chain on a 16 node MP-SoC. Dynamism in the communication is created by the 3D application. On a StrongARM processor clocked at 200 MHz, the allocation time for one time-slot takes about 1000 cycles per hop in the connection. We show that central time-slot allocation algorithms are practical for small-scale MP-SoC systems. Indeed, our algorithm can compute the allocation of 40 connections for a complex scene of the 3D pipeline in 450 to 900 /spl mu/s, depending on the slot table size.
Original languageEnglish
Title of host publicationProceedings of the 3rd Workshop on Embedded Systems for Real-Time Multimedia 2005
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages47-52
Number of pages6
ISBN (Print)0-7803-9347-3
DOIs
Publication statusPublished - 2005
Event3rd Workshop on Embedded Systems for Real-Time Multimedia - New York, United States
Duration: 22 Sep 200523 Sep 2005

Conference

Conference3rd Workshop on Embedded Systems for Real-Time Multimedia
CountryUnited States
CityNew York
Period22/09/0523/09/05

Fingerprint Dive into the research topics of 'Dynamic time-slot allocation for QoS enabled networks on chip.'. Together they form a unique fingerprint.

  • Cite this

    Marescaux, T. M., Bricke, B., Debacker, P., Nollet, V., & Corporaal, H. (2005). Dynamic time-slot allocation for QoS enabled networks on chip. In Proceedings of the 3rd Workshop on Embedded Systems for Real-Time Multimedia 2005 (pp. 47-52). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESTMED.2005.1518069