Abstract
The channel IC described here achieves data rates of 360 Mb/s at performance levels that improve in various directions upon the state of the art. It accomplishes these feats in a mature 1 μm CBiCMOS technology at a read-mode power consumption of only 800 mW. The paper discusses some of the underlying architectural concepts.
| Original language | English |
|---|---|
| Pages (from-to) | 172-177 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Magnetics |
| Volume | 34 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 1 Dec 1998 |
| Externally published | Yes |