One of the main causes of expensive IC redesigns is a failure to meet electromagnetic compatibility (EMC) requirements. For this reason, there is a huge demand for verification methods to identify and prevent immunity failures on chip. Strongly nonlinear effects, in particular DC operating point shifts, are a major cause of such immunity failures. Conventional analysis techniques, used to simulate these strongly nonlinear effects, suffer from a few drawbacks. They can be time-consuming and suffer from convergence issues. Moreover, they do not provide insight into the root causes of the nonlinear behavior. In this paper, an automated method is proposed that overcomes the mentioned drawbacks and identifies causes of immunity failures by listing critical distortion contributions. The method is applicable to very large, strongly nonlinear integrated circuits. It uses a simple model that determines the nonlinear contribution of one device in its linearized environment. Because the computation time is negligible, the analysis can be repeated for many devices and interference frequencies. Additionally, the method gives insight into the drivers responsible for the distortion effects, such that the designer can efficiently solve the problem. The method is demonstrated by applying it to a practical test case.
|Number of pages||13|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - Aug 2020|
Bibliographical noteFunding Information:
Manuscript received November 22, 2019; revised February 21, 2020; accepted March 16, 2020. Date of publication April 15, 2020; date of current version July 31, 2020. This work was supported by the Netherlands Organisation for Scientific Research (NWO, domain AES), under project HTSM 12853.
- Distortion contribution analysis
- electromagnetic compatibility
- harmonic balance
- nonlinear distortion
- polynomial device model
- strongly nonlinear behavior