Abstract
High performance mixed signal (HPMS) platforms require stringent overall system and subsystem performance. The ability to design ultra-low power systems is used in a wide range of platforms including consumer, mobile, identification, healthcare products and microcontrollers. In this paper we present an overview of low power design techniques, challenges and opportunities faced in an industrial research environment. The paper presents strategies on the deployment of low power techniques that span from power-performance optimization scenarios accounting for active and standby operation modes to the development of multi-core architectures suitable for low voltage operation.
| Original language | English |
|---|---|
| Article number | 6766281 |
| Pages (from-to) | 961-975 |
| Number of pages | 15 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 61 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2014 |
Keywords
- Back biasing
- clock tree synthesis (CTS)
- low power
- power gating
- SRAM