Digital signal processing for a sliceable transceiver for optical access networks

Silvia Saldaña Cercos, Christoph Wagner, Juan José Vegas Olmos, Anna Manolova Fagertun, Idelfonso Tafur Monroy

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Methods to upgrade the network infrastructure to cope with current traffic demands has attracted increasing research efforts. A promising alternative is signal slicing. Signal slicing aims at re-using low bandwidth equipment to satisfy high bandwidth traffic demands. This technique has been used also for implementing full signal path symmetry in real-time oscilloscopes to provide performance and signal fidelity (i.e. lower noise and jitter). In this paper the key digital signal processing (DSP) subsystems required to achieve signal slicing are surveyed. It also presents, for the first time, a comprehensive DSP power consumption analysis for both WDM and TDM systems at 1 Gbps and 10 Gbps, discussing latency penalties for each approach. For 1 Gbps WDM system 278 pJ per information bit for 4 slices is reported at 105 ns latency penalties, whereas 3898.4 pJ per information bit at 183.5 μs latency penalty is reported for 10 Gbps. Power savings of the order of hundreds of Watts can be obtained when using signal slicing as an alternative to 10 Gbps implemented access networks.
Original languageEnglish
Title of host publication2015 IEEE Symposium on Computers and Communication (ISCC)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages483-488
Number of pages6
ISBN (Electronic)978-1-4673-7194-0
DOIs
Publication statusPublished - 2015
Externally publishedYes
Event2015 IEEE Symposium on Computers and Communication (ISCC) - Larnaca, Cyprus
Duration: 6 Jul 20159 Jul 2015

Conference

Conference2015 IEEE Symposium on Computers and Communication (ISCC)
CountryCyprus
CityLarnaca
Period6/07/159/07/15

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