A well known problem of time-interleaved analogto-digital converters is the matching between the individual channels of the converter. Any mismatch between the channels affects the accuracy of the converter adversely. The random mismatch between the channels originates mainly from the mismatch of components like transistors and capacitors. To achieve a certain degree of matching between the channels, the sizes of the individual components have to be chosen accordingly. Especially for high-resolution converters, this means that physically large transistors are required, resulting in a large chip area, increased power consumption and reduced conversion speed. Instead of increasing sizes to achieve a certain accuracy, one can also start with an analog circuit that is relatively inaccurate from itself (allowing physically small devices), and use a digital post-correction technique afterwards to correct for the actual deviations of each component. With this method, a high accuracy can be obtained while the requirements for the components are relaxed significantly. Although these techniques have been available for single-channel converters for many years, techniques correcting the mismatch between several channels are scarce. In this paper, an existing algorithm for single-channel pipelined converters is extended to include inter-channel correction as well, requiring almost no additional hardware.
|Title of host publication||Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan|
|Place of Publication||Piscataway, New Jersey, USA|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2005|
|Event||2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan|
Duration: 23 May 2005 → 26 May 2005
|Conference||2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)|
|Abbreviated title||ISCAS 2005|
|Period||23/05/05 → 26/05/05|
Harpe, P. J. A., Zanikopoulos, A., Hegt, J. A., & Roermund, van, A. H. M. (2005). Digital self-correction of time-interleaved ADCs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan (pp. 5541-5544). Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers.