Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs

P.J.A. Harpe; A. Zanikopoulos; J.A. Hegt; A.H.M. Roermund, van

Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs

P.J.A. Harpe
, A. Zanikopoulos
, J.A. Hegt
, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.

Original language	English
Title of host publication	Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece
Place of Publication	Piscataway, New Jersey, USA
Publisher	Institute of Electrical and Electronics Engineers
Pages	1503-1506
Publication status	Published - 2006
Event	2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) - Kos International Convention Centre (KICC), Island of Kos, Greece Duration: 21 May 2006 → 24 May 2006

Conference

Conference	2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
Abbreviated title	ISCAS 2006
Country/Territory	Greece
City	Island of Kos
Period	21/05/06 → 24/05/06

Cite this

@inproceedings{0b5ae16ecbb249f9b0c44a9bf39adaea,

title = "Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs",

abstract = "Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.",

author = "P.J.A. Harpe and A. Zanikopoulos and J.A. Hegt and \{Roermund, van\}, A.H.M.",

year = "2006",

language = "English",

pages = "1503--1506",

booktitle = "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), ISCAS 2006 ; Conference date: 21-05-2006 Through 24-05-2006",

}

Harpe, PJA, Zanikopoulos, A, Hegt, JA & Roermund, van, AHM 2006, Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs. in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, USA, pp. 1503-1506, 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece, 21/05/06.

Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs. / Harpe, P.J.A.; Zanikopoulos, A.; Hegt, J.A. et al.
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece. Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers, 2006. p. 1503-1506.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs

AU - Harpe, P.J.A.

AU - Zanikopoulos, A.

AU - Hegt, J.A.

AU - Roermund, van, A.H.M.

PY - 2006

Y1 - 2006

N2 - Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.

AB - Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.

M3 - Conference contribution

SP - 1503

EP - 1506

BT - Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway, New Jersey, USA

T2 - 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

Y2 - 21 May 2006 through 24 May 2006

ER -

Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs

Abstract

Conference

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