Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs

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Abstract

Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece
Place of PublicationPiscataway, New Jersey, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages1503-1506
Publication statusPublished - 2006
Event2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) - Kos International Convention Centre (KICC), Island of Kos, Greece
Duration: 21 May 200624 May 2006

Conference

Conference2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
Abbreviated titleISCAS 2006
CountryGreece
CityIsland of Kos
Period21/05/0624/05/06

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  • Cite this

    Harpe, P. J. A., Zanikopoulos, A., Hegt, J. A., & Roermund, van, A. H. M. (2006). Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece (pp. 1503-1506). Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers.