Abstract
Abstract-This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to
achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction
algorithm is proposed together with a built-in self-measurement technique.
Original language | English |
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Title of host publication | Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece |
Place of Publication | Piscataway, New Jersey, USA |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1503-1506 |
Publication status | Published - 2006 |
Event | 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) - Kos International Convention Centre (KICC), Island of Kos, Greece Duration: 21 May 2006 → 24 May 2006 |
Conference
Conference | 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) |
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Abbreviated title | ISCAS 2006 |
Country/Territory | Greece |
City | Island of Kos |
Period | 21/05/06 → 24/05/06 |