Digital design update for a sun sensor on a chip

In the beginning of one year project work at Moog-Bradford, the scope of my assignment was coordination of the firmware development activities as defined in the Sun Sensor on a Chip (SSOAC) proposal for ESA GSTP-5 program. As the time progressed in the proposal evaluation process, my project scope had been shifted from ESA SSOAC project to the development activities for the NSO funded PEP mini-Digital Sun Sensor (mini-DSS) project. Objective of this PEP project is to improve the position for the ESA proposal gained by baseline mini-DSS prototype initially designed by TNO. Specifically, my project goal was to implement the firmware related ESA functional requirements in the mini-DSS baseline design. Project activities first started by phasing the project into Definition, Architectural Design, Detailed Design and Prototype Implementation phases. During the project each phase has been carried on sequentially as needed. Initial requirements were evaluated and refined continuously in each consecutive phase. VHDL development activities are carried on to realize selected functional requirements by taking extra care that ESA VHDL modeling guidelines are met in the code and in the documents generated. Specifically, the following results are achieved: • Telemetry design update for sensor unit ID, measurement time-stamp and sensor time check is implemented and verified by simulations and prototyping. • In order to increase reliability, Triple Modular Redundancy (TMR) options are evaluated and implemented together with Single Event Upset (SEU) detection capability in the digital logic. • A fully working simulation, verification and FPGA prototyping environment is set up which will also help the future development efforts especially in system debugging and understanding. • Baseline mini-DSS VHDL code is commented and mismatch between the accompanying design documentation is corrected. In overall, my contribution in this one year project at Moog-Bradford resulted in an updated and improved mini-DSS VHDL model with design documentation and hardware test set-up.