Developing silicon photonics technologies with a wafer-level test station

Jeroen de Coster; Erik Jan Marinissen; Joris van Campenhout; Bryan Bolt; Daniel Rishavy

Developing silicon photonics technologies with a wafer-level test station

Jeroen de Coster
, Erik Jan Marinissen
, Joris van Campenhout
, Bryan Bolt
, Daniel Rishavy

Electronic Systems

Research output: Contribution to journal › Article › Professional

Abstract

Imec and FormFactor present a unique wafer-level test solution that enables semi-automatic testing of passive and active silicon photonics components and circuits.

Original language	English
Journal	imec Magazine
Publication status	Published - 1 Apr 2018

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https://www.imec-int.com/en/imec-magazine/imec-magazine-april-2018/developing-silicon-photonics-technologies-with-a-wafer-level-test-station

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@article{7306641a7d854e54ab0e5cee65be93ab,

title = "Developing silicon photonics technologies with a wafer-level test station",

abstract = "Imec and FormFactor present a unique wafer-level test solution that enables semi-automatic testing of passive and active silicon photonics components and circuits.",

author = "\{de Coster\}, Jeroen and Marinissen, \{Erik Jan\} and \{van Campenhout\}, Joris and Bryan Bolt and Daniel Rishavy",

year = "2018",

month = apr,

day = "1",

language = "English",

journal = "imec Magazine",

publisher = "IMEC",

}

TY - JOUR

T1 - Developing silicon photonics technologies with a wafer-level test station

AU - de Coster, Jeroen

AU - Marinissen, Erik Jan

AU - van Campenhout, Joris

AU - Bolt, Bryan

AU - Rishavy, Daniel

PY - 2018/4/1

Y1 - 2018/4/1

N2 - Imec and FormFactor present a unique wafer-level test solution that enables semi-automatic testing of passive and active silicon photonics components and circuits.

AB - Imec and FormFactor present a unique wafer-level test solution that enables semi-automatic testing of passive and active silicon photonics components and circuits.

M3 - Article

JO - imec Magazine

JF - imec Magazine

ER -

Developing silicon photonics technologies with a wafer-level test station

Abstract

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