Image processing is widely used in many applications, including medical imaging, industrial manufacturing and security systems. In these applications, the size of the image is often very large, the processing time should be very small and the real-time constraints should be met. Therefore, during the last decades, there has been an increasing demand to exploit parallelism in applications. It is possible to explore parallelism along three axes: data-level parallelism (DLP), instruction-level parallelism (ILP) and task-level parallelism (TLP).
This paper explores the limitations and bottlenecks of increasing support for parallelism along the DLP and ILP axes in isolation and in combination. To scrutinize the effect of DLP and ILP in our architecture (template), an area model based on the number of ALUs (ILP) and the number of processing elements (DLP) in the template is defined, as well as a performance model. Based on these models and the template, a set of kernels of image processing applications has been studied to find Pareto optimal architectures in terms of area and number of cycles via multi-objective optimization.
|Title of host publication||Advanced concepts for intelligent vision systems : 7th international conference, ACIVS 2005, Antwerp, Belgium, September 20-23, 2005 : proceedings|
|Editors||J. Blanc-Talon, W. Philips, D. Popescu, P. Scheunders|
|Place of Publication||Berlin|
|Publication status||Published - 2005|
|Event||conference; ACIVS 2005, Antwerp, Belgium; 2005-09-20; 2005-09-23 - |
Duration: 20 Sep 2005 → 23 Sep 2005
|Name||Lecture Notes in Computer Science|
|Conference||conference; ACIVS 2005, Antwerp, Belgium; 2005-09-20; 2005-09-23|
|Period||20/09/05 → 23/09/05|
|Other||ACIVS 2005, Antwerp, Belgium|