Single-chip multi-processor embedded system becomes nowadays a feasible and very interesting option. What is needed however is an environment that supports the designer in transforming an algorithmic specijication into a suitable parallel implementation. In this paper we present and demonstrate an important component of such an environment - an eficient design space exploration algorithm. The algorithm can be used to semi-automatically find the best parallelization of a given embedded application. It employs functional pipelining  and data set partitioning [I 61 simultaneously with source-to-source program transformations to obtain the most advantageous hierarchical parallelizations.
|Title of host publication||Design and Automation Conference 35th (DAC) 15-19 June 1998|
|Publication status||Published - 1998|