Design of a variable gain integrator with reset

M.F. Heertjes, K.G.J. Gruntjens, S.J.L.M. Loon, van, N. Kontaras, W.P.M.H. Heemels

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
9 Downloads (Pure)


This paper studies the properties of a variable gain integrator with reset, i.e. a nonlinear lag filter that is obtained by a) saturating the input, b) filtering the saturated input with a Clegg integrator, and c) add the filtered output to the unsaturated input before applying it to a PID-based controller. Depending on the amount of saturation, the corner frequency of the lag filter is reduced along with the associated phase lag. This follows from a describing function analysis in which at low frequencies a minus 20 dB/decade amplitude decay is realized with a phase lag of only 32.48 degrees. Conditions to assess global asymptotic stability of the closed-loop nonlinear control system are provided that are based on a circle criterion-like argument for the flow condition, which applies to the intervals without resets, combined with a jump condition at reset. The reset integrator design is demonstrated on a piezo-actuated motion system where its favorable phase and amplitude properties induce overshoot and settling times comparable to a single (linear) integrator, but with the disturbance rejection properties of a double integrator.
Original languageEnglish
Title of host publicationProceedings of the 2015 American Control Conference (ACC), 1-3 July 2015, Chicago, Illinois
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)78-1-4799-8685-9
Publication statusPublished - 2015
Event2015 American Control Conference (ACC 2015), July 1–3, 2015, Chicago, IL, USA - Hilton Palmer House, Chicago, IL, United States
Duration: 1 Jul 20153 Jul 2015


Conference2015 American Control Conference (ACC 2015), July 1–3, 2015, Chicago, IL, USA
Abbreviated titleACC 2015
CountryUnited States
CityChicago, IL
Internet address


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