Mechanical resonators are widely applied in time-keeping and frequency reference applications. Mechanical resonators are preferred over electrical resonators because of their high Q. In the $4.1 billion (2008) timing market, quartz crystals are still ubiquitous in electronic equipment. Quartz crystals show excellent performance in terms of stability (shortterm and long-term), power handling, and temperature drift. MEMS resonators are investigated as a potential alternative to the bulky quartz crystals, which cannot be integrated with IC technology. MEMS offer advantages in terms of size, cost price, and system integration. Efforts over recent years have shown that MEMS resonators are able to meet the high performance standards set by quartz. Critical success factors are high Q-factor, low temperature drift, low phase noise, and low power. This PhD thesis addresses the feasibility of scaling MEMS resonators/oscillators to frequencies above 10 MHz. The main deliverable is a 52 MHz MEMS-based oscillator. The MEMS resonators at NXP are processed on 8-inch silicon-on-insulator (SOI) wafers, with a SOI layer thickness of 1.5 µm and a buried oxide layer thickness of 1 µm. The strategic choice for thin SOI substrates has been made for two reasons. First, MEMS processing in thin silicon layers can be done with standard CMOS processing tools. The silicon dioxide layer serves as a sacrificial layer. Second, identical substrates are used for the Advanced Bipolar CMOS DMOS (ABCD) IC-processes. This class of processes can handle high voltages (ABCD2 up to 120V). The high voltage capability is suitable for the transduction of the mechanical resonator. Both MEMS and IC are processed on a similar substrate, since the strategic aim is to integrate the MEMS structure with the IC-process in the long run. Frequency scaling is investigated for both the capacitive and the piezoresistive MEMS resonator. MEMS resonators have been successfully tested from 13 MHz to over 400 MHz. This is achieved by decreasing the size of the resonator with a factor 32. We show that the thin SOI layer and the decreasing size of the resonator increase the effective impedance of the capacitive resonator at higher frequencies. For the piezoresistive resonator, we show that this readout principle is insensitive to geometrical scaling and layer thickness. Therefore, the piezoresistive readout is preferred at high frequencies. The effective impedance can be kept low, at the expense of higher power consumption. Frequency accuracy can be improved by decreasing the initial frequency spread and the temperature drift of the MEMS resonator. The main source of initial frequency spread is geometrical offset, due to the non-perfect pattern transfer from mask layout to SOI. A FEM tool has been developed in Comsol Multiphysics to obtain compensated layouts. The resonance frequency of these designs is first-order compensated for geometric offset. The FEM tool is used to obtain compensated resonators of various designs. We show empirically that the compensation by design is effective on a 52 MHz square plate design. For the compensated design, frequency spread measurements over a complete wafer show that there are other systematic sources of frequency spread. The resonance frequency of the silicon MEMS resonator drifts about –30 ppm/K. This is due to the Young’s modulus of silicon that depends on temperature. We have investigated two compensation methods. The first is passive compensation by coating the silicon resonator with a silicon dioxide skin. The Young’s modulus of silicon dioxide has a positive temperature drift. Measurements on globally oxidized structures show that the right oxide thickness reduces the linear temperature drift of the resonator to zero. A second method uses an oven-control principle. The temperature of the resonator is fixed, independent of the ambient temperature. A demo of this principle has been designed with a piezoresistive resonator in which the dc readout current through the resonator is used to control the temperature of the resonator. With both concepts, more than a factor 10 reduction in temperature drift is achieved. To demonstrate the feasibility of high-frequency oscillators, a MEMS-based 56 MHz oscillator has been designed for which a piezoresistive dogbone resonator is used. The amplifier has been designed in the ABCD2 IC-process. The MEMS oscillator consumes 6.1 mW and exhibits a phase noise of –102 dBc/Hz at 1 kHz offset from the carrier and a floor of –113 dBc/Hz. This demonstrates feasibility of the piezoresistive MEMS oscillator for lowpower, low-noise applications. Summarizing, this PhD thesis work as part of the MEMSXO project at NXP demonstrates a MEMS oscillator concept based on the piezoresistive resonator in thin SOI. It shows that by compensated designs for geometric offset and oven-control to reduce temperature drift, a frequency accuracy can be achieved that can compete with the performance of crystal oscillators. In a benchmark with MEMS competitors the concept shows the lowest phase noise, making it the most suited concept for wireless applications.
|Qualification||Doctor of Philosophy|
|Award date||21 Sep 2009|
|Place of Publication||Eindhoven|
|Publication status||Published - 2009|