Design and Optimization of Multi-bit Front-end Stage and Scaled Back-end Stages of Pipelined ADCs

P.J. Quinn, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

10 Citations (Scopus)

Abstract

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADCs. The paper continues by analyzing the optimal design for low power of the scaled back-end stages. Finally, a model is proposed to estimate the power per stage, and hence total power consumption of the pipeline ADC.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan
Place of PublicationPiscataway, New Jersey, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages1964-1967
ISBN (Print)0-7803-8834-8
Publication statusPublished - 2005
Event2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan
Duration: 23 May 200526 May 2005

Conference

Conference2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)
Abbreviated titleISCAS 2005
CountryJapan
CityKobe
Period23/05/0526/05/05

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