Design and implementation of an algorithmic S2I switched-current multiplier

G. Manganaro; J. Pineda de Gyvez

doi:10.1109/ISCAS.1998.704168

Design and implementation of an algorithmic S2I switched-current multiplier

G. Manganaro, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 µm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 µA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper

Original language	English
Title of host publication	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California
Place of Publication	New York
Publisher	Institute of Electrical and Electronics Engineers
Pages	37-40
Volume	1
ISBN (Print)	0-7803-4455-3
DOIs	https://doi.org/10.1109/ISCAS.1998.704168
Publication status	Published - 1998
Externally published	Yes

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Manganaro, G., & Pineda de Gyvez, J. (1998). Design and implementation of an algorithmic S2I switched-current multiplier. In Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California (Vol. 1, pp. 37-40). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.1998.704168

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abstract = "The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 µm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 µA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper",

author = "G. Manganaro and {Pineda de Gyvez}, J.",

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doi = "10.1109/ISCAS.1998.704168",

language = "English",

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Manganaro, G & Pineda de Gyvez, J 1998, Design and implementation of an algorithmic S2I switched-current multiplier. in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California. vol. 1, Institute of Electrical and Electronics Engineers, New York, pp. 37-40. https://doi.org/10.1109/ISCAS.1998.704168

Design and implementation of an algorithmic S2I switched-current multiplier. / Manganaro, G.; Pineda de Gyvez, J.
Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California. Vol. 1 New York: Institute of Electrical and Electronics Engineers, 1998. p. 37-40.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Design and implementation of an algorithmic S2I switched-current multiplier

AU - Manganaro, G.

AU - Pineda de Gyvez, J.

PY - 1998

Y1 - 1998

N2 - The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 µm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 µA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper

AB - The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 µm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 µA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper

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DO - 10.1109/ISCAS.1998.704168

M3 - Conference contribution

SN - 0-7803-4455-3

VL - 1

SP - 37

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BT - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California

PB - Institute of Electrical and Electronics Engineers

CY - New York

ER -

Design and implementation of an algorithmic S2I switched-current multiplier

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