Design and implementation of an algorithmic S2I switched-current multiplier

G. Manganaro, J. Pineda de Gyvez

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The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 µm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 µA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper
Original languageEnglish
Title of host publicationProceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998, ISCAS '98, 31 may - 3 June 1998, Monterey, California
Place of PublicationNew York
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)0-7803-4455-3
Publication statusPublished - 1998
Externally publishedYes


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