Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

P. Wielage; E.J. Marinissen; M. Altheimer; C. Wouters

doi:10.1109/DATE.2007.364399

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

P. Wielage, E.J. Marinissen, M. Altheimer, C. Wouters

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

20 Citations (Scopus)

Abstract

Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach

Original language	English
Title of host publication	2007 Design, Automation & Test in Europe Conference & Exhibition
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	853-858
Number of pages	6
ISBN (Print)	978-3-9810801-2-4
DOIs	https://doi.org/10.1109/DATE.2007.364399
Publication status	Published - 2007
Externally published	Yes
Event	10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) - Acropolis, Nice, France Duration: 16 Apr 2007 → 20 Apr 2007 Conference number: 10

Conference

Conference	10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007)
Abbreviated title	DATE 2007
Country/Territory	France
City	Nice
Period	16/04/07 → 20/04/07

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10.1109/DATE.2007.364399

Cite this

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title = "Design and DfT of a high-speed area-efficient embedded asynchronous FIFO",

abstract = "Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach",

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Wielage, P, Marinissen, EJ, Altheimer, M & Wouters, C 2007, Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. in 2007 Design, Automation & Test in Europe Conference & Exhibition . Institute of Electrical and Electronics Engineers, Piscataway, pp. 853-858, 10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice, France, 16/04/07. https://doi.org/10.1109/DATE.2007.364399

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. / Wielage, P.; Marinissen, E.J.; Altheimer, M. et al.
2007 Design, Automation & Test in Europe Conference & Exhibition . Piscataway: Institute of Electrical and Electronics Engineers, 2007. p. 853-858.

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

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AU - Marinissen, E.J.

AU - Altheimer, M.

AU - Wouters, C.

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AB - Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach

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ER -

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

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