Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

P. Wielage, E.J. Marinissen, M. Altheimer, C. Wouters

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

20 Citations (Scopus)

Abstract

Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach
Original languageEnglish
Title of host publication2007 Design, Automation & Test in Europe Conference & Exhibition
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages853-858
Number of pages6
ISBN (Print)978-3-9810801-2-4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) - Acropolis, Nice, France
Duration: 16 Apr 200720 Apr 2007
Conference number: 10

Conference

Conference10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007)
Abbreviated titleDATE 2007
CountryFrance
CityNice
Period16/04/0720/04/07

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