Design and analysis of delay-insensitive modulo-N counters

J.C. Ebergen, A.M.G. Peeters

Research output: Contribution to journalArticleAcademicpeer-review

6 Citations (Scopus)


Various delay-insensitive circuits for modulo-N counters are formally derived and analyzed. Modulo-N counters are used in many circuit designs and have a simple specification, but allow for a surprising variety of decompositions into networks of basic components. We present three decompositions in detail. Along the way we explai our correctness criteria and show to analyze the area complexity and response time of each decomposition. Our final decomposition for the modulo-N counter has optimal area complexity of (logN) and optimal response time of (1).
Original languageEnglish
Pages (from-to)211-232
JournalFormal Methods in System Design
Issue number3
Publication statusPublished - 1993

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