Delamination Analysis of Cu/low-k Technology Subjected to Chemical-Mechanical Polishing Process Conditions

C.A. Yuan, W.D. Driel, van, R.B.R. Silfhout, van, O. Sluis, van der, R.A.B. Engelen, L.J. Ernst, F. Keulen, van, G.Q. Zhang

Research output: Contribution to journalArticleAcademicpeer-review

8 Citations (Scopus)

Abstract

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer issimulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possiblegeneration/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.
Original languageEnglish
Pages (from-to)1679-1684
JournalMicroelectronics and Reliability : an International Journal and World Abstracting Service
Volume46
Issue number9-11
DOIs
Publication statusPublished - 2006

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