detailed analog simulation of the cells, and (3) cell-aware automatic test pattern generation (ATPG). This paper focuses on Step 1, as quality and cost are determined by the set of cell-internal defect locations considered in the remainder of the flow. Based on technology inputs from the user and a parasitic extraction (PEX) run that analyzes the cell layouts, we derive a set of open defects on and short defects between both transistor terminals and intra-cell interconnects. The full set of defect locations is stored for later use during failure analysis. Through dedicated DLI algorithms, we identify a compact subset of defect locations for defect characterization and ATPG, in which we include only
one representative defect location for each set of equivalent defects locations. For Cadence’s GPDK045 library, the compact subset contains only 2.8% of the full set of defect locations and reduces the time required for defect characterization with the same ratio.
|Title of host publication||LATS 2019 - 20th IEEE Latin American Test Symposium|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Number of pages||6|
|Publication status||Published - 6 May 2019|
|Event||20th IEEE Latin American Test Symposium, LATS 2019 - Santiago, Chile|
Duration: 11 Mar 2019 → 13 Mar 2019
|Conference||20th IEEE Latin American Test Symposium, LATS 2019|
|Period||11/03/19 → 13/03/19|
- cell-aware test
- defect detection matrix
- parasitic extraction
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Prize: Other › Career, activity or publication related prizes (lifetime, best paper, poster etc.) › Scientific