DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

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Abstract

Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece
Place of PublicationPiscataway, New Jersey, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages101-104
ISBN (Print)0-7803-9389-9
Publication statusPublished - 2006
Event2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) - Kos International Convention Centre (KICC), Island of Kos, Greece
Duration: 21 May 200624 May 2006

Conference

Conference2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
Abbreviated titleISCAS 2006
CountryGreece
CityIsland of Kos
Period21/05/0624/05/06

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    Tang, Y., Hegt, J. A., & Roermund, van, A. H. M. (2006). DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece (pp. 101-104). Institute of Electrical and Electronics Engineers.