DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

Y. Tang; J.A. Hegt; A.H.M. Roermund, van

DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

Y. Tang, J.A. Hegt, A.H.M. Roermund, van

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process.

Original language	English
Title of host publication	Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece
Place of Publication	Piscataway, New Jersey, USA
Publisher	Institute of Electrical and Electronics Engineers
Pages	101-104
ISBN (Print)	0-7803-9389-9
Publication status	Published - 2006
Event	2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006) - Kos International Convention Centre (KICC), Island of Kos, Greece Duration: 21 May 2006 → 24 May 2006

Conference

Conference	2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
Abbreviated title	ISCAS 2006
Country/Territory	Greece
City	Island of Kos
Period	21/05/06 → 24/05/06

Cite this

@inproceedings{cd163a230db44fbea21055bb6b38455f,

title = "DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's",

abstract = "Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process.",

author = "Y. Tang and J.A. Hegt and {Roermund, van}, A.H.M.",

year = "2006",

language = "English",

isbn = "0-7803-9389-9",

pages = "101--104",

booktitle = "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), ISCAS 2006 ; Conference date: 21-05-2006 Through 24-05-2006",

}

Tang, Y, Hegt, JA & Roermund, van, AHM 2006, DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's. in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, USA, pp. 101-104, 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece, 21/05/06.

DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's. / Tang, Y.; Hegt, J.A.; Roermund, van, A.H.M.
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece. Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers, 2006. p. 101-104.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

AU - Tang, Y.

AU - Hegt, J.A.

AU - Roermund, van, A.H.M.

PY - 2006

Y1 - 2006

N2 - Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process.

AB - Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process.

M3 - Conference contribution

SN - 0-7803-9389-9

SP - 101

EP - 104

BT - Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway, New Jersey, USA

T2 - 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

Y2 - 21 May 2006 through 24 May 2006

ER -

DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

Abstract

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