Abstract
Algorithms from many application domains, such as linear algebra and image/signal processing, heavily use the multiplication operator. Despite hardware support which is present in most modern cores, multiplication remains one of the most energy hungry arithmetic operations. This work explores how the energy efficiency of hardware multipliers can be improved by taking into account that the operands of a multiplication typically do not utilize the full width of the datapath. Seven datawidth-aware multiplier designs are implemented and evaluated. Post-layout energy analysis is performed to obtain the energy efficiency of each design for a number of representative benchmarks targeting the consumer market. The results show a significant improvement in energy efficiency compared to a 32-bit Baugh-Wooley baseline multiplier. A 32-bit sign-magnitude based design, integrated in a two's complement datapath, is shown to have a 1.38 times better energy efficiency than a baseline two's complement multiplier. In the best case (JPEG encoding), the energy efficiency is increased by a factor 2.25, demonstrating that a sign-magnitude multiplier, and datawidth-aware multipliers in general, are an attractive option for ultra low-energy designs.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018 |
| Editors | Nikos Konofaos, Martin Novotny, Amund Skavhaug |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 54-61 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-5386-7377-5 |
| ISBN (Print) | 978-1-5386-7378-2 |
| DOIs | |
| Publication status | Published - 12 Oct 2018 |
| Event | 21st Euromicro Conference on Digital System Design, DSD 2018 - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018 Conference number: 21 http://dsd-seaa2018.fit.cvut.cz/dsd/ |
Conference
| Conference | 21st Euromicro Conference on Digital System Design, DSD 2018 |
|---|---|
| Abbreviated title | DSD 2018 |
| Country | Czech Republic |
| City | Prague |
| Period | 29/08/18 → 31/08/18 |
| Internet address |
Fingerprint
Keywords
- Datawidth aware
- Energy efficiency
- Multiplier
- Reduced precision
- Sign magnitude
Cite this
}
Datawidth-aware energy-efficient multipliers : a case for going sign magnitude. / Waeijen, Luc; Jiao, Hailong; Corporaal, Henk; He, Yifan.
Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. ed. / Nikos Konofaos; Martin Novotny; Amund Skavhaug. Piscataway : Institute of Electrical and Electronics Engineers, 2018. p. 54-61 8491795.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Datawidth-aware energy-efficient multipliers
T2 - a case for going sign magnitude
AU - Waeijen, Luc
AU - Jiao, Hailong
AU - Corporaal, Henk
AU - He, Yifan
PY - 2018/10/12
Y1 - 2018/10/12
N2 - Algorithms from many application domains, such as linear algebra and image/signal processing, heavily use the multiplication operator. Despite hardware support which is present in most modern cores, multiplication remains one of the most energy hungry arithmetic operations. This work explores how the energy efficiency of hardware multipliers can be improved by taking into account that the operands of a multiplication typically do not utilize the full width of the datapath. Seven datawidth-aware multiplier designs are implemented and evaluated. Post-layout energy analysis is performed to obtain the energy efficiency of each design for a number of representative benchmarks targeting the consumer market. The results show a significant improvement in energy efficiency compared to a 32-bit Baugh-Wooley baseline multiplier. A 32-bit sign-magnitude based design, integrated in a two's complement datapath, is shown to have a 1.38 times better energy efficiency than a baseline two's complement multiplier. In the best case (JPEG encoding), the energy efficiency is increased by a factor 2.25, demonstrating that a sign-magnitude multiplier, and datawidth-aware multipliers in general, are an attractive option for ultra low-energy designs.
AB - Algorithms from many application domains, such as linear algebra and image/signal processing, heavily use the multiplication operator. Despite hardware support which is present in most modern cores, multiplication remains one of the most energy hungry arithmetic operations. This work explores how the energy efficiency of hardware multipliers can be improved by taking into account that the operands of a multiplication typically do not utilize the full width of the datapath. Seven datawidth-aware multiplier designs are implemented and evaluated. Post-layout energy analysis is performed to obtain the energy efficiency of each design for a number of representative benchmarks targeting the consumer market. The results show a significant improvement in energy efficiency compared to a 32-bit Baugh-Wooley baseline multiplier. A 32-bit sign-magnitude based design, integrated in a two's complement datapath, is shown to have a 1.38 times better energy efficiency than a baseline two's complement multiplier. In the best case (JPEG encoding), the energy efficiency is increased by a factor 2.25, demonstrating that a sign-magnitude multiplier, and datawidth-aware multipliers in general, are an attractive option for ultra low-energy designs.
KW - Datawidth aware
KW - Energy efficiency
KW - Multiplier
KW - Reduced precision
KW - Sign magnitude
UR - http://www.scopus.com/inward/record.url?scp=85056445633&partnerID=8YFLogxK
U2 - 10.1109/DSD.2018.00024
DO - 10.1109/DSD.2018.00024
M3 - Conference contribution
AN - SCOPUS:85056445633
SN - 978-1-5386-7378-2
SP - 54
EP - 61
BT - Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
A2 - Konofaos, Nikos
A2 - Novotny, Martin
A2 - Skavhaug, Amund
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -