Dataflow-based multi-ASIP platform approach for digital control applications

R.M.W. Frijns; A.L.J. Kamp; S. Stuijk; J.P.M. Voeten; M. Bontekoe; K.J.A. Gemei; H. Corporaal

doi:10.1109/DSD.2013.126

Dataflow-based multi-ASIP platform approach for digital control applications

R.M.W. Frijns, A.L.J. Kamp, S. Stuijk, J.P.M. Voeten, M. Bontekoe, K.J.A. Gemei, H. Corporaal

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

To provide a good balance between the performance and flexibility of future digital control platforms, we propose an FPGA-based heterogeneous multiprocessor approach, in which the platform is composed of processing elements from a set of parameterizable heterogeneous Application-Specific Instruction-set Processors (ASIPs), connected with an hierarchical interconnect. With a case-study treating two different industrial-scale controllers, we show that a platform generated from our template using only a small library of instantiable ASIP types outperforms an optimized 8-core general-purpose implementation by a factor 4.9 on sampling frequency and reduces IO-delay with 37.5%.

Original language	English
Title of host publication	Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain
Editors	J. Silva Matos, F. Leporati
Pages	811-814
DOIs	https://doi.org/10.1109/DSD.2013.126
Publication status	Published - 2013
Event	16th Euromicro Conference on Digital System Design (DSD 2013) - Santander, Spain Duration: 4 Sep 2013 → 6 Sep 2013 http://www.teisa.unican.es/dsd-seaa-2013/dsd_2013/index.html%3Fq=node%252F15.html

Conference

Conference	16th Euromicro Conference on Digital System Design (DSD 2013)
Abbreviated title	DSD 2013
Country/Territory	Spain
City	Santander
Period	4/09/13 → 6/09/13
Other	Conference co-located with the 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2013)
Internet address	http://www.teisa.unican.es/dsd-seaa-2013/dsd_2013/index.html%3Fq=node%252F15.html

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10.1109/DSD.2013.126

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Frijns, R. M. W., Kamp, A. L. J., Stuijk, S., Voeten, J. P. M., Bontekoe, M., Gemei, K. J. A., & Corporaal, H. (2013). Dataflow-based multi-ASIP platform approach for digital control applications. In J. Silva Matos, & F. Leporati (Eds.), Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain (pp. 811-814) https://doi.org/10.1109/DSD.2013.126

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title = "Dataflow-based multi-ASIP platform approach for digital control applications",

abstract = "To provide a good balance between the performance and flexibility of future digital control platforms, we propose an FPGA-based heterogeneous multiprocessor approach, in which the platform is composed of processing elements from a set of parameterizable heterogeneous Application-Specific Instruction-set Processors (ASIPs), connected with an hierarchical interconnect. With a case-study treating two different industrial-scale controllers, we show that a platform generated from our template using only a small library of instantiable ASIP types outperforms an optimized 8-core general-purpose implementation by a factor 4.9 on sampling frequency and reduces IO-delay with 37.5%.",

author = "R.M.W. Frijns and A.L.J. Kamp and S. Stuijk and J.P.M. Voeten and M. Bontekoe and K.J.A. Gemei and H. Corporaal",

year = "2013",

doi = "10.1109/DSD.2013.126",

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booktitle = "Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain",

note = "16th Euromicro Conference on Digital System Design (DSD 2013), DSD 2013 ; Conference date: 04-09-2013 Through 06-09-2013",

url = "http://www.teisa.unican.es/dsd-seaa-2013/dsd_2013/index.html%3Fq=node%252F15.html",

}

Frijns, RMW, Kamp, ALJ, Stuijk, S , Voeten, JPM, Bontekoe, M, Gemei, KJA & Corporaal, H 2013, Dataflow-based multi-ASIP platform approach for digital control applications. in J Silva Matos & F Leporati (eds), Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain. pp. 811-814, 16th Euromicro Conference on Digital System Design (DSD 2013), Santander, Spain, 4/09/13. https://doi.org/10.1109/DSD.2013.126

Dataflow-based multi-ASIP platform approach for digital control applications. / Frijns, R.M.W.; Kamp, A.L.J.; Stuijk, S. et al.

Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain. ed. / J. Silva Matos; F. Leporati. 2013. p. 811-814.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Dataflow-based multi-ASIP platform approach for digital control applications

AU - Frijns, R.M.W.

AU - Kamp, A.L.J.

AU - Stuijk, S.

AU - Voeten, J.P.M.

AU - Bontekoe, M.

AU - Gemei, K.J.A.

AU - Corporaal, H.

PY - 2013

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N2 - To provide a good balance between the performance and flexibility of future digital control platforms, we propose an FPGA-based heterogeneous multiprocessor approach, in which the platform is composed of processing elements from a set of parameterizable heterogeneous Application-Specific Instruction-set Processors (ASIPs), connected with an hierarchical interconnect. With a case-study treating two different industrial-scale controllers, we show that a platform generated from our template using only a small library of instantiable ASIP types outperforms an optimized 8-core general-purpose implementation by a factor 4.9 on sampling frequency and reduces IO-delay with 37.5%.

AB - To provide a good balance between the performance and flexibility of future digital control platforms, we propose an FPGA-based heterogeneous multiprocessor approach, in which the platform is composed of processing elements from a set of parameterizable heterogeneous Application-Specific Instruction-set Processors (ASIPs), connected with an hierarchical interconnect. With a case-study treating two different industrial-scale controllers, we show that a platform generated from our template using only a small library of instantiable ASIP types outperforms an optimized 8-core general-purpose implementation by a factor 4.9 on sampling frequency and reduces IO-delay with 37.5%.

U2 - 10.1109/DSD.2013.126

DO - 10.1109/DSD.2013.126

M3 - Conference contribution

SN - 978-0-7695-5074-9

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BT - Proceedings 16th Euromicro Conference on Digital Systems Design (DSD 2013), 4-6 September 2013, Santandor, Spain

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T2 - 16th Euromicro Conference on Digital System Design (DSD 2013)

Y2 - 4 September 2013 through 6 September 2013

ER -

Dataflow-based multi-ASIP platform approach for digital control applications

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