Customization of on-chip network interconnects and experiments in field programmable gate arrays

Jae Young Hur, T. Stefanov, S. Wong, Kees Goossens

Research output: Contribution to journalArticleAcademicpeer-review

9 Citations (Scopus)
2 Downloads (Pure)

Abstract

Conventional rigid and general purpose on-chip networks occupy significant logic and wire resources in field-programmable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.
Original languageEnglish
Pages (from-to)59-68
JournalIET Computers and Digital Techniques
Volume6
Issue number1
DOIs
Publication statusPublished - 2012

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