Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

C. Zhang; L.J. Breems; G.I. Radulov; M. Bolatkale; Qilong Liu; J.A. Hegt; A.H.M. van Roermund

doi:10.1109/ISCAS.2017.8050369

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

C. Zhang, L.J. Breems, G.I. Radulov, M. Bolatkale, Qilong Liu, J.A. Hegt, A.H.M. van Roermund

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

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Abstract

This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is
not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz
MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	547-550
Number of pages	4
ISBN (Electronic)	978-1-4673-6852-0
DOIs	https://doi.org/10.1109/ISCAS.2017.8050369
Publication status	Published - 29 May 2017
Event	2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) - Baltimore, MD, USA, Baltimore, United States Duration: 28 May 2017 → 31 May 2017 Conference number: 50

Conference

Conference	2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017)
Abbreviated title	ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	28/05/17 → 31/05/17

Keywords

Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC

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10.1109/ISCAS.2017.8050369

Cite this

Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A., & van Roermund, A. H. M. (2017). Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. In IEEE International Symposium on Circuits and Systems (pp. 547-550). Article 8050369 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2017.8050369

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title = "Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs",

abstract = "This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.",

keywords = "Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC ",

author = "C. Zhang and L.J. Breems and G.I. Radulov and M. Bolatkale and Qilong Liu and J.A. Hegt and {van Roermund}, A.H.M.",

year = "2017",

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doi = "10.1109/ISCAS.2017.8050369",

language = "English",

pages = "547--550",

booktitle = "IEEE International Symposium on Circuits and Systems",

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Zhang, C, Breems, LJ , Radulov, GI, Bolatkale, M, Liu, Q, Hegt, JA & van Roermund, AHM 2017, Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. in IEEE International Symposium on Circuits and Systems., 8050369, Institute of Electrical and Electronics Engineers, Piscataway, pp. 547-550, 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, United States, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050369

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. / Zhang, C.; Breems, L.J.; Radulov, G.I. et al.
IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, 2017. p. 547-550 8050369.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Breems, L.J.

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AU - Liu, Qilong

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AU - van Roermund, A.H.M.

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N2 - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

AB - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

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Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

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