Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

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Abstract

This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is
not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz
MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages547-550
Number of pages4
ISBN (Electronic)978-1-4673-6852-0
DOIs
Publication statusPublished - 29 May 2017
Event50th IEEE International Symposium on Circuits and Systems (ISCAS 2017) - Baltimore, United States
Duration: 28 May 201731 May 2017

Conference

Conference50th IEEE International Symposium on Circuits and Systems (ISCAS 2017)
Abbreviated titleISCAS 2017
CountryUnited States
CityBaltimore
Period28/05/1731/05/17

Keywords

  • Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC

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