A integrated circuit (100) includes a plurality of cores (110, 120). With each core (110, 120) is associated a TCB (112, 122) for controlling the core in a test mode thereof. Each TCB has a shift register (220) for holding test control data. The TCBs (112, 122) are serially linked in a chain (140) so that, the test control data can be serially shifted in. A system TCB (130) is provided in the chain (140) comprising a further shift register (220). The system TCB (130) is connected to each TCB (112, 122) for, after receiving a particular set of test control data in its shift register (220), providing the TCBs (112, 122) with a system test hold signal for switching between a shift mode and an application mode of the TCBs (112, 122).
|IPC||G01R 31/ 3187 A I|
|Publication status||Published - 9 May 2000|