Core architectures for digital media and the associated compilation techniques

The new generation of multimedia systems will be fully digital. This includes real time digital TV transmission via cable, satellite and terrestrial channels as well as digital audio broadcasting. A number of standards have been developed such as those of the ‘‘Moving Picture Experts Group’’ (MPEG). Those are defined for the source coding of video signals. Various channel coding standards for audio and video transmission based on spread spectrum technology have been established by the ‘‘European Television Standards Institute’’ (ETSI). While the video receivers will come to the market in the form of set top boxes feeding standard PAL-, SECAM- or NTSC-receivers with the appropriate analog signals, a new generation of mobile TV- and radio receivers on the basis of mobile phones and PDA’s is also conceived. One of the central questions regarding the implementation of those products is the balance between flexibility and speed performance of the various hardware-platforms. The competition is between standard processors like the new generations of the Pentium (as ‘‘superscalar’’ representatives), possibly enhanced with add-ons like MMX, or, alternatively, the TRIMEDIA, (a VLIW representative). Somewhere on the scale resided the ‘‘Digital Signal Processors’’ like the TSM 320. But also special purpose architectures like the PROPHID architecture have been developed for applications like multi-channel real time video or real time three dimensional graphics for ‘‘virtual reality’’. Late in the nineties the PROPHID architecture has been cast into an experimental prototype called ‘‘CPA’’ (Coprocessor Array). All those architectures need special software techniques to actually exploit their potential in terms of operation speed. The paper reviews some of the relevant features of the signal streams and the sort of processes that have to be executed on them. Then it discusses some hardware architectures that compete as media-processors. Eventually the question of software design for such architectures is addressed culminating in the description of some recently discovered scheduling techniques to be used in compilers/code generators for those processors