CONVOLVE: Smart and seamless design of smart edge processors

Manil Gomony (Corresponding author), Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank Gurkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexander Jimborean, Sherif EissaLuca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal

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With the rise of DL, our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at ULP, with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well positioned to become leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project addresses these roadblocks. It takes a holistic approach with innovations at all levels of design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting energy-efficiency and flexibility of DL hardware. Finding good solutions is key in making smart-edge computing reality.
Original languageEnglish
Article number2212.00873
Number of pages9
Publication statusPublished - 1 Dec 2022


  • cs.AR


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